273 lines
6.2 KiB
YAML
273 lines
6.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos7 SoC clock controller
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maintainers:
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- Chanwoo Choi <cw00.choi@samsung.com>
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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- Tomasz Figa <tomasz.figa@gmail.com>
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description: |
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Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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name::
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- "fin_pll" - PLL input clock from XXTI
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All available clocks are defined as preprocessor macros in
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include/dt-bindings/clock/exynos7-clk.h header.
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properties:
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compatible:
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enum:
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- samsung,exynos7-clock-topc
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- samsung,exynos7-clock-top0
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- samsung,exynos7-clock-top1
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- samsung,exynos7-clock-ccore
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- samsung,exynos7-clock-peric0
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- samsung,exynos7-clock-peric1
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- samsung,exynos7-clock-peris
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- samsung,exynos7-clock-fsys0
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- samsung,exynos7-clock-fsys1
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- samsung,exynos7-clock-mscl
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- samsung,exynos7-clock-aud
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clocks:
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minItems: 1
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maxItems: 13
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clock-names:
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minItems: 1
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maxItems: 13
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"#clock-cells":
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- "#clock-cells"
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- reg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-top0
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then:
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properties:
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clocks:
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minItems: 6
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maxItems: 6
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clock-names:
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items:
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- const: fin_pll
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- const: dout_sclk_bus0_pll
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- const: dout_sclk_bus1_pll
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- const: dout_sclk_cc_pll
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- const: dout_sclk_mfc_pll
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- const: dout_sclk_aud_pll
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-top1
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then:
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properties:
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clocks:
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minItems: 5
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maxItems: 5
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clock-names:
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items:
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- const: fin_pll
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- const: dout_sclk_bus0_pll
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- const: dout_sclk_bus1_pll
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- const: dout_sclk_cc_pll
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- const: dout_sclk_mfc_pll
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-ccore
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: fin_pll
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- const: dout_aclk_ccore_133
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-peric0
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: fin_pll
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- const: dout_aclk_peric0_66
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- const: sclk_uart0
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-peric1
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then:
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properties:
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clocks:
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minItems: 13
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maxItems: 13
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clock-names:
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items:
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- const: fin_pll
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- const: dout_aclk_peric1_66
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- const: sclk_uart1
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- const: sclk_uart2
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- const: sclk_uart3
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- const: sclk_spi0
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- const: sclk_spi1
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- const: sclk_spi2
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- const: sclk_spi3
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- const: sclk_spi4
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- const: sclk_i2s1
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- const: sclk_pcm1
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- const: sclk_spdif
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-peris
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: fin_pll
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- const: dout_aclk_peris_66
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-fsys0
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: fin_pll
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- const: dout_aclk_fsys0_200
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- const: dout_sclk_mmc2
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-fsys1
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then:
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properties:
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clocks:
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minItems: 7
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maxItems: 7
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clock-names:
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items:
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- const: fin_pll
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- const: dout_aclk_fsys1_200
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- const: dout_sclk_mmc0
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- const: dout_sclk_mmc1
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- const: dout_sclk_ufsunipro20
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- const: dout_sclk_phy_fsys1
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- const: dout_sclk_phy_fsys1_26m
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-clock-aud
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: fin_pll
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- const: fout_aud_pll
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required:
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- clock-names
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos7-clk.h>
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fin_pll: clock {
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compatible = "fixed-clock";
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clock-output-names = "fin_pll";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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clock-controller@105e0000 {
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compatible = "samsung,exynos7-clock-top1";
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reg = <0x105e0000 0xb000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&clock_topc DOUT_SCLK_BUS0_PLL>,
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<&clock_topc DOUT_SCLK_BUS1_PLL>,
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<&clock_topc DOUT_SCLK_CC_PLL>,
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<&clock_topc DOUT_SCLK_MFC_PLL>;
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clock-names = "fin_pll",
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"dout_sclk_bus0_pll",
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"dout_sclk_bus1_pll",
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"dout_sclk_cc_pll",
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"dout_sclk_mfc_pll";
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};
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