74 lines
1.8 KiB
YAML
74 lines
1.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ROCKCHIP rk3568 Family Clock Control Module
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maintainers:
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- Elaine Zhang <zhangqing@rock-chips.com>
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- Heiko Stuebner <heiko@sntech.de>
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description: |
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The RK3568 clock controller generates the clock and also implements a
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reset controller for SoC peripherals.
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(examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for UART module)
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
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used in device tree sources.
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properties:
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compatible:
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enum:
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- rockchip,rk3568-cru
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- rockchip,rk3568-pmucru
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reg:
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maxItems: 1
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"#clock-cells":
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const: 1
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"#reset-cells":
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const: 1
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clocks:
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maxItems: 1
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clock-names:
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const: xin24m
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rockchip,grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon managing the "general register files" (GRF),
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if missing pll rates are not changeable, due to the missing pll
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lock status.
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required:
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- compatible
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- reg
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- "#clock-cells"
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- "#reset-cells"
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additionalProperties: false
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examples:
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# Clock Control Module node:
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- |
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pmucru: clock-controller@fdd00000 {
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compatible = "rockchip,rk3568-pmucru";
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reg = <0xfdd00000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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- |
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cru: clock-controller@fdd20000 {
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compatible = "rockchip,rk3568-cru";
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reg = <0xfdd20000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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