70 lines
1.5 KiB
YAML
70 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm6115-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock Controller for SM6115
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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description: |
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Qualcomm display clock control module provides the clocks and power domains
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on SM6115.
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See also:: include/dt-bindings/clock/qcom,sm6115-dispcc.h
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properties:
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compatible:
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enum:
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- qcom,sm6115-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: Board sleep clock
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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- description: GPLL0 DISP DIV clock from GCC
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,gcc-sm6115.h>
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clock-controller@5f00000 {
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compatible = "qcom,sm6115-dispcc";
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reg = <0x5f00000 0x20000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&sleep_clk>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>,
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<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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