69 lines
1.8 KiB
YAML
69 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000
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maintainers:
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- Taniya Das <quic_tdas@quicinc.com>
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- Imran Shaik <quic_imrashai@quicinc.com>
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description: |
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Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control
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module which supports the clocks, resets on QDU1000 and QRU1000
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See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
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properties:
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compatible:
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enum:
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- qcom,qdu1000-ecpricc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 source from GCC
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- description: GPLL1 source from GCC
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- description: GPLL2 source from GCC
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- description: GPLL3 source from GCC
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- description: GPLL4 source from GCC
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- description: GPLL5 source from GCC
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,qdu1000-gcc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@280000 {
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compatible = "qcom,qdu1000-ecpricc";
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reg = <0x00280000 0x31c00>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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