81 lines
1.7 KiB
C
81 lines
1.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Broadcom BCM63xx Processor Monitor Bus shared routines (SMP and reset)
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*
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* Copyright (C) 2015, Broadcom Corporation
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* Author: Florian Fainelli <f.fainelli@gmail.com>
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*/
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#ifndef __BCM63XX_PMB_H
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#define __BCM63XX_PMB_H
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#include <linux/io.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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/* PMB Master controller register */
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#define PMB_CTRL 0x00
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#define PMC_PMBM_START (1 << 31)
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#define PMC_PMBM_TIMEOUT (1 << 30)
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#define PMC_PMBM_SLAVE_ERR (1 << 29)
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#define PMC_PMBM_BUSY (1 << 28)
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#define PMC_PMBM_READ (0 << 20)
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#define PMC_PMBM_WRITE (1 << 20)
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#define PMB_WR_DATA 0x04
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#define PMB_TIMEOUT 0x08
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#define PMB_RD_DATA 0x0C
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#define PMB_BUS_ID_SHIFT 8
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/* Perform the low-level PMB master operation, shared between reads and
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* writes.
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*/
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static inline int __bpcm_do_op(void __iomem *master, unsigned int addr,
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u32 off, u32 op)
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{
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unsigned int timeout = 1000;
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u32 cmd;
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cmd = (PMC_PMBM_START | op | (addr & 0xff) << 12 | off);
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writel(cmd, master + PMB_CTRL);
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do {
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cmd = readl(master + PMB_CTRL);
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if (!(cmd & PMC_PMBM_START))
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return 0;
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if (cmd & PMC_PMBM_SLAVE_ERR)
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return -EIO;
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if (cmd & PMC_PMBM_TIMEOUT)
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return -ETIMEDOUT;
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udelay(1);
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} while (timeout-- > 0);
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return -ETIMEDOUT;
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}
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static inline int bpcm_rd(void __iomem *master, unsigned int addr,
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u32 off, u32 *val)
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{
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int ret = 0;
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ret = __bpcm_do_op(master, addr, off >> 2, PMC_PMBM_READ);
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*val = readl(master + PMB_RD_DATA);
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return ret;
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}
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static inline int bpcm_wr(void __iomem *master, unsigned int addr,
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u32 off, u32 val)
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{
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int ret = 0;
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writel(val, master + PMB_WR_DATA);
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ret = __bpcm_do_op(master, addr, off >> 2, PMC_PMBM_WRITE);
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return ret;
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}
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#endif /* __BCM63XX_PMB_H */
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