681 lines
15 KiB
C
681 lines
15 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/device.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/nvmem-provider.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/random.h>
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#include <soc/tegra/fuse.h>
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#include "fuse.h"
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#define FUSE_BEGIN 0x100
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/* Tegra30 and later */
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#define FUSE_VENDOR_CODE 0x100
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#define FUSE_FAB_CODE 0x104
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#define FUSE_LOT_CODE_0 0x108
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#define FUSE_LOT_CODE_1 0x10c
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#define FUSE_WAFER_ID 0x110
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#define FUSE_X_COORDINATE 0x114
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#define FUSE_Y_COORDINATE 0x118
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#define FUSE_HAS_REVISION_INFO BIT(0)
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#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
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defined(CONFIG_ARCH_TEGRA_114_SOC) || \
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defined(CONFIG_ARCH_TEGRA_124_SOC) || \
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defined(CONFIG_ARCH_TEGRA_132_SOC) || \
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defined(CONFIG_ARCH_TEGRA_210_SOC) || \
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defined(CONFIG_ARCH_TEGRA_186_SOC) || \
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defined(CONFIG_ARCH_TEGRA_194_SOC) || \
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defined(CONFIG_ARCH_TEGRA_234_SOC)
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static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
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{
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if (WARN_ON(!fuse->base))
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return 0;
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return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
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}
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static u32 tegra30_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
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{
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u32 value;
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int err;
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err = pm_runtime_resume_and_get(fuse->dev);
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if (err)
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return 0;
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value = readl_relaxed(fuse->base + FUSE_BEGIN + offset);
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pm_runtime_put(fuse->dev);
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return value;
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}
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static void __init tegra30_fuse_add_randomness(void)
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{
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u32 randomness[12];
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randomness[0] = tegra_sku_info.sku_id;
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randomness[1] = tegra_read_straps();
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randomness[2] = tegra_read_chipid();
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randomness[3] = tegra_sku_info.cpu_process_id << 16;
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randomness[3] |= tegra_sku_info.soc_process_id;
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randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
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randomness[4] |= tegra_sku_info.soc_speedo_id;
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randomness[5] = tegra_fuse_read_early(FUSE_VENDOR_CODE);
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randomness[6] = tegra_fuse_read_early(FUSE_FAB_CODE);
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randomness[7] = tegra_fuse_read_early(FUSE_LOT_CODE_0);
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randomness[8] = tegra_fuse_read_early(FUSE_LOT_CODE_1);
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randomness[9] = tegra_fuse_read_early(FUSE_WAFER_ID);
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randomness[10] = tegra_fuse_read_early(FUSE_X_COORDINATE);
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randomness[11] = tegra_fuse_read_early(FUSE_Y_COORDINATE);
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add_device_randomness(randomness, sizeof(randomness));
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}
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static void __init tegra30_fuse_init(struct tegra_fuse *fuse)
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{
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fuse->read_early = tegra30_fuse_read_early;
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fuse->read = tegra30_fuse_read;
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tegra_init_revision();
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if (fuse->soc->speedo_init)
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fuse->soc->speedo_init(&tegra_sku_info);
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tegra30_fuse_add_randomness();
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}
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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static const struct tegra_fuse_info tegra30_fuse_info = {
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.read = tegra30_fuse_read,
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.size = 0x2a4,
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.spare = 0x144,
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};
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const struct tegra_fuse_soc tegra30_fuse_soc = {
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.init = tegra30_fuse_init,
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.speedo_init = tegra30_init_speedo_data,
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.info = &tegra30_fuse_info,
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.soc_attr_group = &tegra_soc_attr_group,
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.clk_suspend_on = false,
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};
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#endif
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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static const struct tegra_fuse_info tegra114_fuse_info = {
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.read = tegra30_fuse_read,
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.size = 0x2a0,
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.spare = 0x180,
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};
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const struct tegra_fuse_soc tegra114_fuse_soc = {
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.init = tegra30_fuse_init,
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.speedo_init = tegra114_init_speedo_data,
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.info = &tegra114_fuse_info,
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.soc_attr_group = &tegra_soc_attr_group,
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.clk_suspend_on = false,
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};
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#endif
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#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
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static const struct nvmem_cell_info tegra124_fuse_cells[] = {
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{
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.name = "tsensor-cpu1",
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.offset = 0x084,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-cpu2",
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.offset = 0x088,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-cpu0",
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.offset = 0x098,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "xusb-pad-calibration",
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.offset = 0x0f0,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-cpu3",
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.offset = 0x12c,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "sata-calibration",
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.offset = 0x124,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-gpu",
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.offset = 0x154,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-mem0",
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.offset = 0x158,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-mem1",
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.offset = 0x15c,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-pllx",
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.offset = 0x160,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-common",
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.offset = 0x180,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-realignment",
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.offset = 0x1fc,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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},
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};
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static const struct nvmem_cell_lookup tegra124_fuse_lookups[] = {
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{
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.nvmem_name = "fuse",
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.cell_name = "xusb-pad-calibration",
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.dev_id = "7009f000.padctl",
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.con_id = "calibration",
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}, {
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.nvmem_name = "fuse",
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.cell_name = "sata-calibration",
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.dev_id = "70020000.sata",
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.con_id = "calibration",
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}, {
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.nvmem_name = "fuse",
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.cell_name = "tsensor-common",
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.dev_id = "700e2000.thermal-sensor",
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.con_id = "common",
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}, {
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.nvmem_name = "fuse",
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.cell_name = "tsensor-realignment",
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.dev_id = "700e2000.thermal-sensor",
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.con_id = "realignment",
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}, {
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.nvmem_name = "fuse",
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.cell_name = "tsensor-cpu0",
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.dev_id = "700e2000.thermal-sensor",
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.con_id = "cpu0",
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}, {
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.nvmem_name = "fuse",
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.cell_name = "tsensor-cpu1",
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.dev_id = "700e2000.thermal-sensor",
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.con_id = "cpu1",
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}, {
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.nvmem_name = "fuse",
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.cell_name = "tsensor-cpu2",
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.dev_id = "700e2000.thermal-sensor",
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.con_id = "cpu2",
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}, {
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.nvmem_name = "fuse",
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.cell_name = "tsensor-cpu3",
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.dev_id = "700e2000.thermal-sensor",
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.con_id = "cpu3",
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}, {
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.nvmem_name = "fuse",
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.cell_name = "tsensor-mem0",
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.dev_id = "700e2000.thermal-sensor",
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.con_id = "mem0",
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}, {
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.nvmem_name = "fuse",
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.cell_name = "tsensor-mem1",
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.dev_id = "700e2000.thermal-sensor",
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.con_id = "mem1",
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}, {
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.nvmem_name = "fuse",
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.cell_name = "tsensor-gpu",
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.dev_id = "700e2000.thermal-sensor",
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.con_id = "gpu",
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}, {
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.nvmem_name = "fuse",
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.cell_name = "tsensor-pllx",
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.dev_id = "700e2000.thermal-sensor",
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.con_id = "pllx",
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},
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};
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static const struct tegra_fuse_info tegra124_fuse_info = {
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.read = tegra30_fuse_read,
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.size = 0x300,
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.spare = 0x200,
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};
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const struct tegra_fuse_soc tegra124_fuse_soc = {
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.init = tegra30_fuse_init,
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.speedo_init = tegra124_init_speedo_data,
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.info = &tegra124_fuse_info,
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.lookups = tegra124_fuse_lookups,
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.num_lookups = ARRAY_SIZE(tegra124_fuse_lookups),
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.cells = tegra124_fuse_cells,
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.num_cells = ARRAY_SIZE(tegra124_fuse_cells),
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.soc_attr_group = &tegra_soc_attr_group,
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.clk_suspend_on = true,
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};
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#endif
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#if defined(CONFIG_ARCH_TEGRA_210_SOC)
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static const struct nvmem_cell_info tegra210_fuse_cells[] = {
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{
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.name = "tsensor-cpu1",
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.offset = 0x084,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-cpu2",
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.offset = 0x088,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-cpu0",
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.offset = 0x098,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "xusb-pad-calibration",
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.offset = 0x0f0,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-cpu3",
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.offset = 0x12c,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "sata-calibration",
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.offset = 0x124,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-gpu",
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.offset = 0x154,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-mem0",
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.offset = 0x158,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-mem1",
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.offset = 0x15c,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-pllx",
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.offset = 0x160,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "tsensor-common",
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.offset = 0x180,
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.bytes = 4,
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.bit_offset = 0,
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.nbits = 32,
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}, {
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.name = "gpu-calibration",
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.offset = 0x204,
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.bytes = 4,
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.bit_offset = 0,
|
||
|
|
.nbits = 32,
|
||
|
|
}, {
|
||
|
|
.name = "xusb-pad-calibration-ext",
|
||
|
|
.offset = 0x250,
|
||
|
|
.bytes = 4,
|
||
|
|
.bit_offset = 0,
|
||
|
|
.nbits = 32,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct nvmem_cell_lookup tegra210_fuse_lookups[] = {
|
||
|
|
{
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "tsensor-cpu1",
|
||
|
|
.dev_id = "700e2000.thermal-sensor",
|
||
|
|
.con_id = "cpu1",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "tsensor-cpu2",
|
||
|
|
.dev_id = "700e2000.thermal-sensor",
|
||
|
|
.con_id = "cpu2",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "tsensor-cpu0",
|
||
|
|
.dev_id = "700e2000.thermal-sensor",
|
||
|
|
.con_id = "cpu0",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "xusb-pad-calibration",
|
||
|
|
.dev_id = "7009f000.padctl",
|
||
|
|
.con_id = "calibration",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "tsensor-cpu3",
|
||
|
|
.dev_id = "700e2000.thermal-sensor",
|
||
|
|
.con_id = "cpu3",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "sata-calibration",
|
||
|
|
.dev_id = "70020000.sata",
|
||
|
|
.con_id = "calibration",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "tsensor-gpu",
|
||
|
|
.dev_id = "700e2000.thermal-sensor",
|
||
|
|
.con_id = "gpu",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "tsensor-mem0",
|
||
|
|
.dev_id = "700e2000.thermal-sensor",
|
||
|
|
.con_id = "mem0",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "tsensor-mem1",
|
||
|
|
.dev_id = "700e2000.thermal-sensor",
|
||
|
|
.con_id = "mem1",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "tsensor-pllx",
|
||
|
|
.dev_id = "700e2000.thermal-sensor",
|
||
|
|
.con_id = "pllx",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "tsensor-common",
|
||
|
|
.dev_id = "700e2000.thermal-sensor",
|
||
|
|
.con_id = "common",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "gpu-calibration",
|
||
|
|
.dev_id = "57000000.gpu",
|
||
|
|
.con_id = "calibration",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "xusb-pad-calibration-ext",
|
||
|
|
.dev_id = "7009f000.padctl",
|
||
|
|
.con_id = "calibration-ext",
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct tegra_fuse_info tegra210_fuse_info = {
|
||
|
|
.read = tegra30_fuse_read,
|
||
|
|
.size = 0x300,
|
||
|
|
.spare = 0x280,
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct tegra_fuse_soc tegra210_fuse_soc = {
|
||
|
|
.init = tegra30_fuse_init,
|
||
|
|
.speedo_init = tegra210_init_speedo_data,
|
||
|
|
.info = &tegra210_fuse_info,
|
||
|
|
.lookups = tegra210_fuse_lookups,
|
||
|
|
.cells = tegra210_fuse_cells,
|
||
|
|
.num_cells = ARRAY_SIZE(tegra210_fuse_cells),
|
||
|
|
.num_lookups = ARRAY_SIZE(tegra210_fuse_lookups),
|
||
|
|
.soc_attr_group = &tegra_soc_attr_group,
|
||
|
|
.clk_suspend_on = false,
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(CONFIG_ARCH_TEGRA_186_SOC)
|
||
|
|
static const struct nvmem_cell_info tegra186_fuse_cells[] = {
|
||
|
|
{
|
||
|
|
.name = "xusb-pad-calibration",
|
||
|
|
.offset = 0x0f0,
|
||
|
|
.bytes = 4,
|
||
|
|
.bit_offset = 0,
|
||
|
|
.nbits = 32,
|
||
|
|
}, {
|
||
|
|
.name = "xusb-pad-calibration-ext",
|
||
|
|
.offset = 0x250,
|
||
|
|
.bytes = 4,
|
||
|
|
.bit_offset = 0,
|
||
|
|
.nbits = 32,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct nvmem_cell_lookup tegra186_fuse_lookups[] = {
|
||
|
|
{
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "xusb-pad-calibration",
|
||
|
|
.dev_id = "3520000.padctl",
|
||
|
|
.con_id = "calibration",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "xusb-pad-calibration-ext",
|
||
|
|
.dev_id = "3520000.padctl",
|
||
|
|
.con_id = "calibration-ext",
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct nvmem_keepout tegra186_fuse_keepouts[] = {
|
||
|
|
{ .start = 0x01c, .end = 0x0f0 },
|
||
|
|
{ .start = 0x138, .end = 0x198 },
|
||
|
|
{ .start = 0x1d8, .end = 0x250 },
|
||
|
|
{ .start = 0x280, .end = 0x290 },
|
||
|
|
{ .start = 0x340, .end = 0x344 }
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct tegra_fuse_info tegra186_fuse_info = {
|
||
|
|
.read = tegra30_fuse_read,
|
||
|
|
.size = 0x478,
|
||
|
|
.spare = 0x280,
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct tegra_fuse_soc tegra186_fuse_soc = {
|
||
|
|
.init = tegra30_fuse_init,
|
||
|
|
.info = &tegra186_fuse_info,
|
||
|
|
.lookups = tegra186_fuse_lookups,
|
||
|
|
.num_lookups = ARRAY_SIZE(tegra186_fuse_lookups),
|
||
|
|
.cells = tegra186_fuse_cells,
|
||
|
|
.num_cells = ARRAY_SIZE(tegra186_fuse_cells),
|
||
|
|
.keepouts = tegra186_fuse_keepouts,
|
||
|
|
.num_keepouts = ARRAY_SIZE(tegra186_fuse_keepouts),
|
||
|
|
.soc_attr_group = &tegra_soc_attr_group,
|
||
|
|
.clk_suspend_on = false,
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(CONFIG_ARCH_TEGRA_194_SOC)
|
||
|
|
static const struct nvmem_cell_info tegra194_fuse_cells[] = {
|
||
|
|
{
|
||
|
|
.name = "xusb-pad-calibration",
|
||
|
|
.offset = 0x0f0,
|
||
|
|
.bytes = 4,
|
||
|
|
.bit_offset = 0,
|
||
|
|
.nbits = 32,
|
||
|
|
}, {
|
||
|
|
.name = "gpu-gcplex-config-fuse",
|
||
|
|
.offset = 0x1c8,
|
||
|
|
.bytes = 4,
|
||
|
|
.bit_offset = 0,
|
||
|
|
.nbits = 32,
|
||
|
|
}, {
|
||
|
|
.name = "xusb-pad-calibration-ext",
|
||
|
|
.offset = 0x250,
|
||
|
|
.bytes = 4,
|
||
|
|
.bit_offset = 0,
|
||
|
|
.nbits = 32,
|
||
|
|
}, {
|
||
|
|
.name = "gpu-pdi0",
|
||
|
|
.offset = 0x300,
|
||
|
|
.bytes = 4,
|
||
|
|
.bit_offset = 0,
|
||
|
|
.nbits = 32,
|
||
|
|
}, {
|
||
|
|
.name = "gpu-pdi1",
|
||
|
|
.offset = 0x304,
|
||
|
|
.bytes = 4,
|
||
|
|
.bit_offset = 0,
|
||
|
|
.nbits = 32,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = {
|
||
|
|
{
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "xusb-pad-calibration",
|
||
|
|
.dev_id = "3520000.padctl",
|
||
|
|
.con_id = "calibration",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "xusb-pad-calibration-ext",
|
||
|
|
.dev_id = "3520000.padctl",
|
||
|
|
.con_id = "calibration-ext",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "gpu-gcplex-config-fuse",
|
||
|
|
.dev_id = "17000000.gpu",
|
||
|
|
.con_id = "gcplex-config-fuse",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "gpu-pdi0",
|
||
|
|
.dev_id = "17000000.gpu",
|
||
|
|
.con_id = "pdi0",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "gpu-pdi1",
|
||
|
|
.dev_id = "17000000.gpu",
|
||
|
|
.con_id = "pdi1",
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct nvmem_keepout tegra194_fuse_keepouts[] = {
|
||
|
|
{ .start = 0x01c, .end = 0x0b8 },
|
||
|
|
{ .start = 0x12c, .end = 0x198 },
|
||
|
|
{ .start = 0x1a0, .end = 0x1bc },
|
||
|
|
{ .start = 0x1d8, .end = 0x250 },
|
||
|
|
{ .start = 0x270, .end = 0x290 },
|
||
|
|
{ .start = 0x310, .end = 0x45c }
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct tegra_fuse_info tegra194_fuse_info = {
|
||
|
|
.read = tegra30_fuse_read,
|
||
|
|
.size = 0x650,
|
||
|
|
.spare = 0x280,
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct tegra_fuse_soc tegra194_fuse_soc = {
|
||
|
|
.init = tegra30_fuse_init,
|
||
|
|
.info = &tegra194_fuse_info,
|
||
|
|
.lookups = tegra194_fuse_lookups,
|
||
|
|
.num_lookups = ARRAY_SIZE(tegra194_fuse_lookups),
|
||
|
|
.cells = tegra194_fuse_cells,
|
||
|
|
.num_cells = ARRAY_SIZE(tegra194_fuse_cells),
|
||
|
|
.keepouts = tegra194_fuse_keepouts,
|
||
|
|
.num_keepouts = ARRAY_SIZE(tegra194_fuse_keepouts),
|
||
|
|
.soc_attr_group = &tegra194_soc_attr_group,
|
||
|
|
.clk_suspend_on = false,
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(CONFIG_ARCH_TEGRA_234_SOC)
|
||
|
|
static const struct nvmem_cell_info tegra234_fuse_cells[] = {
|
||
|
|
{
|
||
|
|
.name = "xusb-pad-calibration",
|
||
|
|
.offset = 0x0f0,
|
||
|
|
.bytes = 4,
|
||
|
|
.bit_offset = 0,
|
||
|
|
.nbits = 32,
|
||
|
|
}, {
|
||
|
|
.name = "xusb-pad-calibration-ext",
|
||
|
|
.offset = 0x250,
|
||
|
|
.bytes = 4,
|
||
|
|
.bit_offset = 0,
|
||
|
|
.nbits = 32,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct nvmem_cell_lookup tegra234_fuse_lookups[] = {
|
||
|
|
{
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "xusb-pad-calibration",
|
||
|
|
.dev_id = "3520000.padctl",
|
||
|
|
.con_id = "calibration",
|
||
|
|
}, {
|
||
|
|
.nvmem_name = "fuse",
|
||
|
|
.cell_name = "xusb-pad-calibration-ext",
|
||
|
|
.dev_id = "3520000.padctl",
|
||
|
|
.con_id = "calibration-ext",
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct nvmem_keepout tegra234_fuse_keepouts[] = {
|
||
|
|
{ .start = 0x01c, .end = 0x0c8 },
|
||
|
|
{ .start = 0x12c, .end = 0x184 },
|
||
|
|
{ .start = 0x190, .end = 0x198 },
|
||
|
|
{ .start = 0x1a0, .end = 0x204 },
|
||
|
|
{ .start = 0x21c, .end = 0x250 },
|
||
|
|
{ .start = 0x25c, .end = 0x2f0 },
|
||
|
|
{ .start = 0x310, .end = 0x3d8 },
|
||
|
|
{ .start = 0x400, .end = 0x4f0 },
|
||
|
|
{ .start = 0x4f8, .end = 0x7e8 },
|
||
|
|
{ .start = 0x8d0, .end = 0x8d8 },
|
||
|
|
{ .start = 0xacc, .end = 0xf00 }
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct tegra_fuse_info tegra234_fuse_info = {
|
||
|
|
.read = tegra30_fuse_read,
|
||
|
|
.size = 0xf90,
|
||
|
|
.spare = 0x280,
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct tegra_fuse_soc tegra234_fuse_soc = {
|
||
|
|
.init = tegra30_fuse_init,
|
||
|
|
.info = &tegra234_fuse_info,
|
||
|
|
.lookups = tegra234_fuse_lookups,
|
||
|
|
.num_lookups = ARRAY_SIZE(tegra234_fuse_lookups),
|
||
|
|
.cells = tegra234_fuse_cells,
|
||
|
|
.num_cells = ARRAY_SIZE(tegra234_fuse_cells),
|
||
|
|
.keepouts = tegra234_fuse_keepouts,
|
||
|
|
.num_keepouts = ARRAY_SIZE(tegra234_fuse_keepouts),
|
||
|
|
.soc_attr_group = &tegra194_soc_attr_group,
|
||
|
|
.clk_suspend_on = false,
|
||
|
|
};
|
||
|
|
#endif
|