241 lines
6.3 KiB
C
241 lines
6.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* This file contains platform specific structure definitions
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* and init function used by Cannon Lake Point PCH.
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*
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* Copyright (c) 2022, Intel Corporation.
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* All Rights Reserved.
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*
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*/
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#include "core.h"
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/* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */
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const struct pmc_bit_map cnp_pfear_map[] = {
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{"PMC", BIT(0)},
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{"OPI-DMI", BIT(1)},
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{"SPI/eSPI", BIT(2)},
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{"XHCI", BIT(3)},
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{"SPA", BIT(4)},
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{"SPB", BIT(5)},
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{"SPC", BIT(6)},
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{"GBE", BIT(7)},
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{"SATA", BIT(0)},
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{"HDA_PGD0", BIT(1)},
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{"HDA_PGD1", BIT(2)},
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{"HDA_PGD2", BIT(3)},
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{"HDA_PGD3", BIT(4)},
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{"SPD", BIT(5)},
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{"LPSS", BIT(6)},
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{"LPC", BIT(7)},
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{"SMB", BIT(0)},
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{"ISH", BIT(1)},
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{"P2SB", BIT(2)},
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{"NPK_VNN", BIT(3)},
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{"SDX", BIT(4)},
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{"SPE", BIT(5)},
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{"Fuse", BIT(6)},
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{"SBR8", BIT(7)},
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{"CSME_FSC", BIT(0)},
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{"USB3_OTG", BIT(1)},
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{"EXI", BIT(2)},
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{"CSE", BIT(3)},
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{"CSME_KVM", BIT(4)},
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{"CSME_PMT", BIT(5)},
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{"CSME_CLINK", BIT(6)},
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{"CSME_PTIO", BIT(7)},
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{"CSME_USBR", BIT(0)},
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{"CSME_SUSRAM", BIT(1)},
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{"CSME_SMT1", BIT(2)},
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{"CSME_SMT4", BIT(3)},
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{"CSME_SMS2", BIT(4)},
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{"CSME_SMS1", BIT(5)},
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{"CSME_RTC", BIT(6)},
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{"CSME_PSF", BIT(7)},
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{"SBR0", BIT(0)},
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{"SBR1", BIT(1)},
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{"SBR2", BIT(2)},
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{"SBR3", BIT(3)},
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{"SBR4", BIT(4)},
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{"SBR5", BIT(5)},
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{"CSME_PECI", BIT(6)},
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{"PSF1", BIT(7)},
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{"PSF2", BIT(0)},
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{"PSF3", BIT(1)},
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{"PSF4", BIT(2)},
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{"CNVI", BIT(3)},
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{"UFS0", BIT(4)},
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{"EMMC", BIT(5)},
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{"SPF", BIT(6)},
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{"SBR6", BIT(7)},
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{"SBR7", BIT(0)},
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{"NPK_AON", BIT(1)},
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{"HDA_PGD4", BIT(2)},
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{"HDA_PGD5", BIT(3)},
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{"HDA_PGD6", BIT(4)},
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{"PSF6", BIT(5)},
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{"PSF7", BIT(6)},
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{"PSF8", BIT(7)},
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{}
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};
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const struct pmc_bit_map *ext_cnp_pfear_map[] = {
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/*
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* Check intel_pmc_core_ids[] users of cnp_reg_map for
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* a list of core SoCs using this.
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*/
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cnp_pfear_map,
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NULL
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};
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const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
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{"AUDIO_D3", BIT(0)},
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{"OTG_D3", BIT(1)},
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{"XHCI_D3", BIT(2)},
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{"LPIO_D3", BIT(3)},
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{"SDX_D3", BIT(4)},
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{"SATA_D3", BIT(5)},
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{"UFS0_D3", BIT(6)},
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{"UFS1_D3", BIT(7)},
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{"EMMC_D3", BIT(8)},
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{}
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};
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const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
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{"SDIO_PLL_OFF", BIT(0)},
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{"USB2_PLL_OFF", BIT(1)},
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{"AUDIO_PLL_OFF", BIT(2)},
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{"OC_PLL_OFF", BIT(3)},
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{"MAIN_PLL_OFF", BIT(4)},
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{"XOSC_OFF", BIT(5)},
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{"LPC_CLKS_GATED", BIT(6)},
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{"PCIE_CLKREQS_IDLE", BIT(7)},
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{"AUDIO_ROSC_OFF", BIT(8)},
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{"HPET_XOSC_CLK_REQ", BIT(9)},
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{"PMC_ROSC_SLOW_CLK", BIT(10)},
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{"AON2_ROSC_GATED", BIT(11)},
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{"CLKACKS_DEASSERTED", BIT(12)},
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{}
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};
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const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
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{"MPHY_CORE_GATED", BIT(0)},
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{"CSME_GATED", BIT(1)},
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{"USB2_SUS_GATED", BIT(2)},
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{"DYN_FLEX_IO_IDLE", BIT(3)},
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{"GBE_NO_LINK", BIT(4)},
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{"THERM_SEN_DISABLED", BIT(5)},
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{"PCIE_LOW_POWER", BIT(6)},
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{"ISH_VNNAON_REQ_ACT", BIT(7)},
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{"ISH_VNN_REQ_ACT", BIT(8)},
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{"CNV_VNNAON_REQ_ACT", BIT(9)},
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{"CNV_VNN_REQ_ACT", BIT(10)},
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{"NPK_VNNON_REQ_ACT", BIT(11)},
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{"PMSYNC_STATE_IDLE", BIT(12)},
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{"ALST_GT_THRES", BIT(13)},
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{"PMC_ARC_PG_READY", BIT(14)},
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{}
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};
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const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
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cnp_slps0_dbg0_map,
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cnp_slps0_dbg1_map,
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cnp_slps0_dbg2_map,
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NULL
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};
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const struct pmc_bit_map cnp_ltr_show_map[] = {
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{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
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{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
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{"SATA", CNP_PMC_LTR_SATA},
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{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
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{"XHCI", CNP_PMC_LTR_XHCI},
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{"Reserved", CNP_PMC_LTR_RESERVED},
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{"ME", CNP_PMC_LTR_ME},
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/* EVA is Enterprise Value Add, doesn't really exist on PCH */
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{"EVA", CNP_PMC_LTR_EVA},
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{"SOUTHPORT_C", CNP_PMC_LTR_SPC},
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{"HD_AUDIO", CNP_PMC_LTR_AZ},
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{"CNV", CNP_PMC_LTR_CNV},
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{"LPSS", CNP_PMC_LTR_LPSS},
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{"SOUTHPORT_D", CNP_PMC_LTR_SPD},
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{"SOUTHPORT_E", CNP_PMC_LTR_SPE},
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{"CAMERA", CNP_PMC_LTR_CAM},
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{"ESPI", CNP_PMC_LTR_ESPI},
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{"SCC", CNP_PMC_LTR_SCC},
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{"ISH", CNP_PMC_LTR_ISH},
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{"UFSX2", CNP_PMC_LTR_UFSX2},
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{"EMMC", CNP_PMC_LTR_EMMC},
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/*
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* Check intel_pmc_core_ids[] users of cnp_reg_map for
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* a list of core SoCs using this.
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*/
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{"WIGIG", ICL_PMC_LTR_WIGIG},
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{"THC0", TGL_PMC_LTR_THC0},
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{"THC1", TGL_PMC_LTR_THC1},
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/* Below two cannot be used for LTR_IGNORE */
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{"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
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{"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
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{}
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};
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const struct pmc_reg_map cnp_reg_map = {
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.pfear_sts = ext_cnp_pfear_map,
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.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
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.slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
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.slps0_dbg_maps = cnp_slps0_dbg_maps,
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.ltr_show_sts = cnp_ltr_show_map,
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.msr_sts = msr_map,
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.slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
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.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
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.regmap_length = CNP_PMC_MMIO_REG_LEN,
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.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
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.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
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.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
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.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
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.ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
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.etr3_offset = ETR3_OFFSET,
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};
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void cnl_suspend(struct pmc_dev *pmcdev)
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{
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/*
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* Due to a hardware limitation, the GBE LTR blocks PC10
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* when a cable is attached. To unblock PC10 during suspend,
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* tell the PMC to ignore it.
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*/
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pmc_core_send_ltr_ignore(pmcdev, 3, 1);
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}
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int cnl_resume(struct pmc_dev *pmcdev)
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{
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pmc_core_send_ltr_ignore(pmcdev, 3, 0);
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return pmc_core_resume_common(pmcdev);
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}
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int cnp_core_init(struct pmc_dev *pmcdev)
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{
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struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
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int ret;
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pmcdev->suspend = cnl_suspend;
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pmcdev->resume = cnl_resume;
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pmc->map = &cnp_reg_map;
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ret = get_primary_reg_base(pmc);
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if (ret)
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return ret;
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pmc_core_get_low_power_modes(pmcdev);
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return 0;
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}
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