100 lines
2.9 KiB
C
100 lines
2.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2022 Richtek Technology Corp.
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*
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* Author: ChiYuan Huang <cy_huang@richtek.com>
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*/
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#ifndef __MFD_MT6370_H__
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#define __MFD_MT6370_H__
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/* IRQ definitions */
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#define MT6370_IRQ_DIRCHGON 0
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#define MT6370_IRQ_CHG_TREG 4
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#define MT6370_IRQ_CHG_AICR 5
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#define MT6370_IRQ_CHG_MIVR 6
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#define MT6370_IRQ_PWR_RDY 7
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#define MT6370_IRQ_FL_CHG_VINOVP 11
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#define MT6370_IRQ_CHG_VSYSUV 12
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#define MT6370_IRQ_CHG_VSYSOV 13
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#define MT6370_IRQ_CHG_VBATOV 14
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#define MT6370_IRQ_CHG_VINOVPCHG 15
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#define MT6370_IRQ_TS_BAT_COLD 20
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#define MT6370_IRQ_TS_BAT_COOL 21
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#define MT6370_IRQ_TS_BAT_WARM 22
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#define MT6370_IRQ_TS_BAT_HOT 23
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#define MT6370_IRQ_TS_STATC 24
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#define MT6370_IRQ_CHG_FAULT 25
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#define MT6370_IRQ_CHG_STATC 26
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#define MT6370_IRQ_CHG_TMR 27
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#define MT6370_IRQ_CHG_BATABS 28
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#define MT6370_IRQ_CHG_ADPBAD 29
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#define MT6370_IRQ_CHG_RVP 30
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#define MT6370_IRQ_TSHUTDOWN 31
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#define MT6370_IRQ_CHG_IINMEAS 32
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#define MT6370_IRQ_CHG_ICCMEAS 33
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#define MT6370_IRQ_CHGDET_DONE 34
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#define MT6370_IRQ_WDTMR 35
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#define MT6370_IRQ_SSFINISH 36
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#define MT6370_IRQ_CHG_RECHG 37
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#define MT6370_IRQ_CHG_TERM 38
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#define MT6370_IRQ_CHG_IEOC 39
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#define MT6370_IRQ_ADC_DONE 40
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#define MT6370_IRQ_PUMPX_DONE 41
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#define MT6370_IRQ_BST_BATUV 45
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#define MT6370_IRQ_BST_MIDOV 46
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#define MT6370_IRQ_BST_OLP 47
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#define MT6370_IRQ_ATTACH 48
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#define MT6370_IRQ_DETACH 49
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#define MT6370_IRQ_HVDCP_STPDONE 51
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#define MT6370_IRQ_HVDCP_VBUSDET_DONE 52
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#define MT6370_IRQ_HVDCP_DET 53
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#define MT6370_IRQ_CHGDET 54
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#define MT6370_IRQ_DCDT 55
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#define MT6370_IRQ_DIRCHG_VGOK 59
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#define MT6370_IRQ_DIRCHG_WDTMR 60
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#define MT6370_IRQ_DIRCHG_UC 61
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#define MT6370_IRQ_DIRCHG_OC 62
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#define MT6370_IRQ_DIRCHG_OV 63
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#define MT6370_IRQ_OVPCTRL_SWON 67
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#define MT6370_IRQ_OVPCTRL_UVP_D 68
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#define MT6370_IRQ_OVPCTRL_UVP 69
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#define MT6370_IRQ_OVPCTRL_OVP_D 70
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#define MT6370_IRQ_OVPCTRL_OVP 71
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#define MT6370_IRQ_FLED_STRBPIN 72
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#define MT6370_IRQ_FLED_TORPIN 73
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#define MT6370_IRQ_FLED_TX 74
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#define MT6370_IRQ_FLED_LVF 75
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#define MT6370_IRQ_FLED2_SHORT 78
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#define MT6370_IRQ_FLED1_SHORT 79
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#define MT6370_IRQ_FLED2_STRB 80
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#define MT6370_IRQ_FLED1_STRB 81
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#define mT6370_IRQ_FLED2_STRB_TO 82
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#define MT6370_IRQ_FLED1_STRB_TO 83
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#define MT6370_IRQ_FLED2_TOR 84
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#define MT6370_IRQ_FLED1_TOR 85
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#define MT6370_IRQ_OTP 93
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#define MT6370_IRQ_VDDA_OVP 94
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#define MT6370_IRQ_VDDA_UV 95
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#define MT6370_IRQ_LDO_OC 103
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#define MT6370_IRQ_BLED_OCP 118
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#define MT6370_IRQ_BLED_OVP 119
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#define MT6370_IRQ_DSV_VNEG_OCP 123
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#define MT6370_IRQ_DSV_VPOS_OCP 124
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#define MT6370_IRQ_DSV_BST_OCP 125
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#define MT6370_IRQ_DSV_VNEG_SCP 126
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#define MT6370_IRQ_DSV_VPOS_SCP 127
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enum {
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MT6370_USBC_I2C = 0,
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MT6370_PMU_I2C,
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MT6370_MAX_I2C
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};
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struct mt6370_info {
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struct i2c_client *i2c[MT6370_MAX_I2C];
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struct regmap_irq_chip_data *irq_data;
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};
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#endif /* __MFD_MT6375_H__ */
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