457 lines
12 KiB
C
457 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* MAX10 BMC Platform Management Component Interface (PMCI) based
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* interface.
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*
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* Copyright (C) 2020-2023 Intel Corporation.
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*/
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#include <linux/bitfield.h>
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#include <linux/device.h>
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#include <linux/dfl.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/intel-m10-bmc.h>
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#include <linux/minmax.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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struct m10bmc_pmci_device {
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void __iomem *base;
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struct intel_m10bmc m10bmc;
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struct mutex flash_mutex; /* protects flash_busy and serializes flash read/read */
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bool flash_busy;
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};
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/*
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* Intel FGPA indirect register access via hardware controller/bridge.
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*/
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#define INDIRECT_CMD_OFF 0
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#define INDIRECT_CMD_CLR 0
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#define INDIRECT_CMD_RD BIT(0)
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#define INDIRECT_CMD_WR BIT(1)
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#define INDIRECT_CMD_ACK BIT(2)
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#define INDIRECT_ADDR_OFF 0x4
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#define INDIRECT_RD_OFF 0x8
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#define INDIRECT_WR_OFF 0xc
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#define INDIRECT_INT_US 1
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#define INDIRECT_TIMEOUT_US 10000
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struct indirect_ctx {
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void __iomem *base;
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struct device *dev;
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};
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static int indirect_clear_cmd(struct indirect_ctx *ctx)
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{
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unsigned int cmd;
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int ret;
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writel(INDIRECT_CMD_CLR, ctx->base + INDIRECT_CMD_OFF);
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ret = readl_poll_timeout(ctx->base + INDIRECT_CMD_OFF, cmd,
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cmd == INDIRECT_CMD_CLR,
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INDIRECT_INT_US, INDIRECT_TIMEOUT_US);
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if (ret)
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dev_err(ctx->dev, "timed out waiting clear cmd (residual cmd=0x%x)\n", cmd);
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return ret;
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}
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static int indirect_reg_read(void *context, unsigned int reg, unsigned int *val)
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{
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struct indirect_ctx *ctx = context;
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unsigned int cmd, ack, tmpval;
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int ret, ret2;
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cmd = readl(ctx->base + INDIRECT_CMD_OFF);
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if (cmd != INDIRECT_CMD_CLR)
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dev_warn(ctx->dev, "residual cmd 0x%x on read entry\n", cmd);
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writel(reg, ctx->base + INDIRECT_ADDR_OFF);
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writel(INDIRECT_CMD_RD, ctx->base + INDIRECT_CMD_OFF);
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ret = readl_poll_timeout(ctx->base + INDIRECT_CMD_OFF, ack,
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(ack & INDIRECT_CMD_ACK) == INDIRECT_CMD_ACK,
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INDIRECT_INT_US, INDIRECT_TIMEOUT_US);
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if (ret)
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dev_err(ctx->dev, "read timed out on reg 0x%x ack 0x%x\n", reg, ack);
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else
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tmpval = readl(ctx->base + INDIRECT_RD_OFF);
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ret2 = indirect_clear_cmd(ctx);
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if (ret)
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return ret;
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if (ret2)
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return ret2;
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*val = tmpval;
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return 0;
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}
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static int indirect_reg_write(void *context, unsigned int reg, unsigned int val)
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{
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struct indirect_ctx *ctx = context;
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unsigned int cmd, ack;
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int ret, ret2;
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cmd = readl(ctx->base + INDIRECT_CMD_OFF);
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if (cmd != INDIRECT_CMD_CLR)
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dev_warn(ctx->dev, "residual cmd 0x%x on write entry\n", cmd);
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writel(val, ctx->base + INDIRECT_WR_OFF);
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writel(reg, ctx->base + INDIRECT_ADDR_OFF);
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writel(INDIRECT_CMD_WR, ctx->base + INDIRECT_CMD_OFF);
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ret = readl_poll_timeout(ctx->base + INDIRECT_CMD_OFF, ack,
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(ack & INDIRECT_CMD_ACK) == INDIRECT_CMD_ACK,
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INDIRECT_INT_US, INDIRECT_TIMEOUT_US);
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if (ret)
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dev_err(ctx->dev, "write timed out on reg 0x%x ack 0x%x\n", reg, ack);
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ret2 = indirect_clear_cmd(ctx);
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if (ret)
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return ret;
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return ret2;
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}
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static void pmci_write_fifo(void __iomem *base, const u32 *buf, size_t count)
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{
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while (count--)
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writel(*buf++, base);
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}
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static void pmci_read_fifo(void __iomem *base, u32 *buf, size_t count)
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{
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while (count--)
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*buf++ = readl(base);
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}
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static u32 pmci_get_write_space(struct m10bmc_pmci_device *pmci)
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{
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u32 val;
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int ret;
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ret = read_poll_timeout(readl, val,
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FIELD_GET(M10BMC_N6000_FLASH_FIFO_SPACE, val) ==
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M10BMC_N6000_FIFO_MAX_WORDS,
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M10BMC_FLASH_INT_US, M10BMC_FLASH_TIMEOUT_US,
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false, pmci->base + M10BMC_N6000_FLASH_CTRL);
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if (ret == -ETIMEDOUT)
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return 0;
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return FIELD_GET(M10BMC_N6000_FLASH_FIFO_SPACE, val) * M10BMC_N6000_FIFO_WORD_SIZE;
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}
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static int pmci_flash_bulk_write(struct intel_m10bmc *m10bmc, const u8 *buf, u32 size)
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{
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struct m10bmc_pmci_device *pmci = container_of(m10bmc, struct m10bmc_pmci_device, m10bmc);
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u32 blk_size, offset = 0, write_count;
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while (size) {
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blk_size = min(pmci_get_write_space(pmci), size);
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if (blk_size == 0) {
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dev_err(m10bmc->dev, "get FIFO available size fail\n");
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return -EIO;
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}
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if (size < M10BMC_N6000_FIFO_WORD_SIZE)
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break;
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write_count = blk_size / M10BMC_N6000_FIFO_WORD_SIZE;
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pmci_write_fifo(pmci->base + M10BMC_N6000_FLASH_FIFO,
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(u32 *)(buf + offset), write_count);
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size -= blk_size;
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offset += blk_size;
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}
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/* Handle remainder (less than M10BMC_N6000_FIFO_WORD_SIZE bytes) */
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if (size) {
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u32 tmp = 0;
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memcpy(&tmp, buf + offset, size);
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pmci_write_fifo(pmci->base + M10BMC_N6000_FLASH_FIFO, &tmp, 1);
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}
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return 0;
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}
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static int pmci_flash_bulk_read(struct intel_m10bmc *m10bmc, u8 *buf, u32 addr, u32 size)
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{
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struct m10bmc_pmci_device *pmci = container_of(m10bmc, struct m10bmc_pmci_device, m10bmc);
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u32 blk_size, offset = 0, val, full_read_count, read_count;
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int ret;
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while (size) {
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blk_size = min_t(u32, size, M10BMC_N6000_READ_BLOCK_SIZE);
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full_read_count = blk_size / M10BMC_N6000_FIFO_WORD_SIZE;
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read_count = full_read_count;
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if (full_read_count * M10BMC_N6000_FIFO_WORD_SIZE < blk_size)
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read_count++;
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writel(addr + offset, pmci->base + M10BMC_N6000_FLASH_ADDR);
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writel(FIELD_PREP(M10BMC_N6000_FLASH_READ_COUNT, read_count) |
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M10BMC_N6000_FLASH_RD_MODE,
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pmci->base + M10BMC_N6000_FLASH_CTRL);
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ret = readl_poll_timeout((pmci->base + M10BMC_N6000_FLASH_CTRL), val,
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!(val & M10BMC_N6000_FLASH_BUSY),
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M10BMC_FLASH_INT_US, M10BMC_FLASH_TIMEOUT_US);
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if (ret) {
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dev_err(m10bmc->dev, "read timed out on reading flash 0x%xn", val);
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return ret;
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}
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pmci_read_fifo(pmci->base + M10BMC_N6000_FLASH_FIFO,
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(u32 *)(buf + offset), full_read_count);
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size -= blk_size;
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offset += blk_size;
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if (full_read_count < read_count)
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break;
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writel(0, pmci->base + M10BMC_N6000_FLASH_CTRL);
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}
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/* Handle remainder (less than M10BMC_N6000_FIFO_WORD_SIZE bytes) */
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if (size) {
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u32 tmp;
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pmci_read_fifo(pmci->base + M10BMC_N6000_FLASH_FIFO, &tmp, 1);
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memcpy(buf + offset, &tmp, size);
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writel(0, pmci->base + M10BMC_N6000_FLASH_CTRL);
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}
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return 0;
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}
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static int m10bmc_pmci_set_flash_host_mux(struct intel_m10bmc *m10bmc, bool request)
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{
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u32 ctrl;
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int ret;
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ret = regmap_update_bits(m10bmc->regmap, M10BMC_N6000_FLASH_MUX_CTRL,
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M10BMC_N6000_FLASH_HOST_REQUEST,
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FIELD_PREP(M10BMC_N6000_FLASH_HOST_REQUEST, request));
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if (ret)
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return ret;
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return regmap_read_poll_timeout(m10bmc->regmap,
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M10BMC_N6000_FLASH_MUX_CTRL, ctrl,
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request ?
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(get_flash_mux(ctrl) == M10BMC_N6000_FLASH_MUX_HOST) :
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(get_flash_mux(ctrl) != M10BMC_N6000_FLASH_MUX_HOST),
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M10BMC_FLASH_INT_US, M10BMC_FLASH_TIMEOUT_US);
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}
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static int m10bmc_pmci_flash_read(struct intel_m10bmc *m10bmc, u8 *buf, u32 addr, u32 size)
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{
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struct m10bmc_pmci_device *pmci = container_of(m10bmc, struct m10bmc_pmci_device, m10bmc);
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int ret, ret2;
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mutex_lock(&pmci->flash_mutex);
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if (pmci->flash_busy) {
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ret = -EBUSY;
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goto unlock;
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}
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ret = m10bmc_pmci_set_flash_host_mux(m10bmc, true);
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if (ret)
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goto mux_fail;
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ret = pmci_flash_bulk_read(m10bmc, buf, addr, size);
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mux_fail:
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ret2 = m10bmc_pmci_set_flash_host_mux(m10bmc, false);
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unlock:
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mutex_unlock(&pmci->flash_mutex);
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if (ret)
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return ret;
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return ret2;
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}
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static int m10bmc_pmci_flash_write(struct intel_m10bmc *m10bmc, const u8 *buf, u32 offset, u32 size)
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{
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struct m10bmc_pmci_device *pmci = container_of(m10bmc, struct m10bmc_pmci_device, m10bmc);
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int ret;
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mutex_lock(&pmci->flash_mutex);
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WARN_ON_ONCE(!pmci->flash_busy);
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/* On write, firmware manages flash MUX */
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ret = pmci_flash_bulk_write(m10bmc, buf + offset, size);
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mutex_unlock(&pmci->flash_mutex);
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return ret;
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}
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static int m10bmc_pmci_flash_lock(struct intel_m10bmc *m10bmc)
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{
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struct m10bmc_pmci_device *pmci = container_of(m10bmc, struct m10bmc_pmci_device, m10bmc);
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int ret = 0;
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mutex_lock(&pmci->flash_mutex);
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if (pmci->flash_busy) {
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ret = -EBUSY;
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goto unlock;
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}
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pmci->flash_busy = true;
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unlock:
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mutex_unlock(&pmci->flash_mutex);
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return ret;
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}
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static void m10bmc_pmci_flash_unlock(struct intel_m10bmc *m10bmc)
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{
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struct m10bmc_pmci_device *pmci = container_of(m10bmc, struct m10bmc_pmci_device, m10bmc);
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mutex_lock(&pmci->flash_mutex);
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WARN_ON_ONCE(!pmci->flash_busy);
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pmci->flash_busy = false;
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mutex_unlock(&pmci->flash_mutex);
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}
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static const struct intel_m10bmc_flash_bulk_ops m10bmc_pmci_flash_bulk_ops = {
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.read = m10bmc_pmci_flash_read,
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.write = m10bmc_pmci_flash_write,
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.lock_write = m10bmc_pmci_flash_lock,
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.unlock_write = m10bmc_pmci_flash_unlock,
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};
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static const struct regmap_range m10bmc_pmci_regmap_range[] = {
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regmap_reg_range(M10BMC_N6000_SYS_BASE, M10BMC_N6000_SYS_END),
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};
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static const struct regmap_access_table m10bmc_pmci_access_table = {
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.yes_ranges = m10bmc_pmci_regmap_range,
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.n_yes_ranges = ARRAY_SIZE(m10bmc_pmci_regmap_range),
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};
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static struct regmap_config m10bmc_pmci_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.wr_table = &m10bmc_pmci_access_table,
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.rd_table = &m10bmc_pmci_access_table,
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.reg_read = &indirect_reg_read,
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.reg_write = &indirect_reg_write,
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.max_register = M10BMC_N6000_SYS_END,
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};
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static struct mfd_cell m10bmc_pmci_n6000_bmc_subdevs[] = {
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||
|
|
{ .name = "n6000bmc-hwmon" },
|
||
|
|
{ .name = "n6000bmc-sec-update" },
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct m10bmc_csr_map m10bmc_n6000_csr_map = {
|
||
|
|
.base = M10BMC_N6000_SYS_BASE,
|
||
|
|
.build_version = M10BMC_N6000_BUILD_VER,
|
||
|
|
.fw_version = NIOS2_N6000_FW_VERSION,
|
||
|
|
.mac_low = M10BMC_N6000_MAC_LOW,
|
||
|
|
.mac_high = M10BMC_N6000_MAC_HIGH,
|
||
|
|
.doorbell = M10BMC_N6000_DOORBELL,
|
||
|
|
.auth_result = M10BMC_N6000_AUTH_RESULT,
|
||
|
|
.bmc_prog_addr = M10BMC_N6000_BMC_PROG_ADDR,
|
||
|
|
.bmc_reh_addr = M10BMC_N6000_BMC_REH_ADDR,
|
||
|
|
.bmc_magic = M10BMC_N6000_BMC_PROG_MAGIC,
|
||
|
|
.sr_prog_addr = M10BMC_N6000_SR_PROG_ADDR,
|
||
|
|
.sr_reh_addr = M10BMC_N6000_SR_REH_ADDR,
|
||
|
|
.sr_magic = M10BMC_N6000_SR_PROG_MAGIC,
|
||
|
|
.pr_prog_addr = M10BMC_N6000_PR_PROG_ADDR,
|
||
|
|
.pr_reh_addr = M10BMC_N6000_PR_REH_ADDR,
|
||
|
|
.pr_magic = M10BMC_N6000_PR_PROG_MAGIC,
|
||
|
|
.rsu_update_counter = M10BMC_N6000_STAGING_FLASH_COUNT,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct intel_m10bmc_platform_info m10bmc_pmci_n6000 = {
|
||
|
|
.cells = m10bmc_pmci_n6000_bmc_subdevs,
|
||
|
|
.n_cells = ARRAY_SIZE(m10bmc_pmci_n6000_bmc_subdevs),
|
||
|
|
.csr_map = &m10bmc_n6000_csr_map,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int m10bmc_pmci_probe(struct dfl_device *ddev)
|
||
|
|
{
|
||
|
|
struct device *dev = &ddev->dev;
|
||
|
|
struct m10bmc_pmci_device *pmci;
|
||
|
|
struct indirect_ctx *ctx;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
pmci = devm_kzalloc(dev, sizeof(*pmci), GFP_KERNEL);
|
||
|
|
if (!pmci)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
pmci->m10bmc.flash_bulk_ops = &m10bmc_pmci_flash_bulk_ops;
|
||
|
|
pmci->m10bmc.dev = dev;
|
||
|
|
|
||
|
|
pmci->base = devm_ioremap_resource(dev, &ddev->mmio_res);
|
||
|
|
if (IS_ERR(pmci->base))
|
||
|
|
return PTR_ERR(pmci->base);
|
||
|
|
|
||
|
|
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
|
||
|
|
if (!ctx)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
mutex_init(&pmci->flash_mutex);
|
||
|
|
|
||
|
|
ctx->base = pmci->base + M10BMC_N6000_INDIRECT_BASE;
|
||
|
|
ctx->dev = dev;
|
||
|
|
indirect_clear_cmd(ctx);
|
||
|
|
pmci->m10bmc.regmap = devm_regmap_init(dev, NULL, ctx, &m10bmc_pmci_regmap_config);
|
||
|
|
|
||
|
|
if (IS_ERR(pmci->m10bmc.regmap)) {
|
||
|
|
ret = PTR_ERR(pmci->m10bmc.regmap);
|
||
|
|
goto destroy_mutex;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = m10bmc_dev_init(&pmci->m10bmc, &m10bmc_pmci_n6000);
|
||
|
|
if (ret)
|
||
|
|
goto destroy_mutex;
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
destroy_mutex:
|
||
|
|
mutex_destroy(&pmci->flash_mutex);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void m10bmc_pmci_remove(struct dfl_device *ddev)
|
||
|
|
{
|
||
|
|
struct intel_m10bmc *m10bmc = dev_get_drvdata(&ddev->dev);
|
||
|
|
struct m10bmc_pmci_device *pmci = container_of(m10bmc, struct m10bmc_pmci_device, m10bmc);
|
||
|
|
|
||
|
|
mutex_destroy(&pmci->flash_mutex);
|
||
|
|
}
|
||
|
|
|
||
|
|
#define FME_FEATURE_ID_M10BMC_PMCI 0x12
|
||
|
|
|
||
|
|
static const struct dfl_device_id m10bmc_pmci_ids[] = {
|
||
|
|
{ FME_ID, FME_FEATURE_ID_M10BMC_PMCI },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(dfl, m10bmc_pmci_ids);
|
||
|
|
|
||
|
|
static struct dfl_driver m10bmc_pmci_driver = {
|
||
|
|
.drv = {
|
||
|
|
.name = "intel-m10-bmc",
|
||
|
|
.dev_groups = m10bmc_dev_groups,
|
||
|
|
},
|
||
|
|
.id_table = m10bmc_pmci_ids,
|
||
|
|
.probe = m10bmc_pmci_probe,
|
||
|
|
.remove = m10bmc_pmci_remove,
|
||
|
|
};
|
||
|
|
|
||
|
|
module_dfl_driver(m10bmc_pmci_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("MAX10 BMC PMCI-based interface");
|
||
|
|
MODULE_AUTHOR("Intel Corporation");
|
||
|
|
MODULE_LICENSE("GPL");
|
||
|
|
MODULE_IMPORT_NS(INTEL_M10_BMC_CORE);
|