297 lines
7.0 KiB
C
297 lines
7.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* DDR Self-Refresh Power Down (SRPD) support for Broadcom STB SoCs
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*
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#define REG_MEMC_CNTRLR_CONFIG 0x00
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#define CNTRLR_CONFIG_LPDDR4_SHIFT 5
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#define CNTRLR_CONFIG_MASK 0xf
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#define REG_MEMC_SRPD_CFG_21 0x20
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#define REG_MEMC_SRPD_CFG_20 0x34
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#define REG_MEMC_SRPD_CFG_1x 0x3c
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#define INACT_COUNT_SHIFT 0
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#define INACT_COUNT_MASK 0xffff
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#define SRPD_EN_SHIFT 16
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struct brcmstb_memc_data {
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u32 srpd_offset;
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};
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struct brcmstb_memc {
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struct device *dev;
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void __iomem *ddr_ctrl;
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unsigned int timeout_cycles;
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u32 frequency;
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u32 srpd_offset;
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};
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static int brcmstb_memc_uses_lpddr4(struct brcmstb_memc *memc)
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{
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void __iomem *config = memc->ddr_ctrl + REG_MEMC_CNTRLR_CONFIG;
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u32 reg;
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reg = readl_relaxed(config) & CNTRLR_CONFIG_MASK;
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return reg == CNTRLR_CONFIG_LPDDR4_SHIFT;
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}
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static int brcmstb_memc_srpd_config(struct brcmstb_memc *memc,
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unsigned int cycles)
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{
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void __iomem *cfg = memc->ddr_ctrl + memc->srpd_offset;
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u32 val;
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/* Max timeout supported in HW */
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if (cycles > INACT_COUNT_MASK)
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return -EINVAL;
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memc->timeout_cycles = cycles;
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val = (cycles << INACT_COUNT_SHIFT) & INACT_COUNT_MASK;
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if (cycles)
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val |= BIT(SRPD_EN_SHIFT);
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writel_relaxed(val, cfg);
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/* Ensure the write is committed to the controller */
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(void)readl_relaxed(cfg);
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return 0;
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}
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static ssize_t frequency_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct brcmstb_memc *memc = dev_get_drvdata(dev);
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return sprintf(buf, "%d\n", memc->frequency);
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}
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static ssize_t srpd_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct brcmstb_memc *memc = dev_get_drvdata(dev);
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return sprintf(buf, "%d\n", memc->timeout_cycles);
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}
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static ssize_t srpd_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct brcmstb_memc *memc = dev_get_drvdata(dev);
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unsigned int val;
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int ret;
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/*
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* Cannot change the inactivity timeout on LPDDR4 chips because the
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* dynamic tuning process will also get affected by the inactivity
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* timeout, thus making it non functional.
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*/
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if (brcmstb_memc_uses_lpddr4(memc))
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return -EOPNOTSUPP;
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ret = kstrtouint(buf, 10, &val);
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if (ret < 0)
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return ret;
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ret = brcmstb_memc_srpd_config(memc, val);
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if (ret)
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return ret;
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return count;
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}
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static DEVICE_ATTR_RO(frequency);
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static DEVICE_ATTR_RW(srpd);
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static struct attribute *dev_attrs[] = {
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&dev_attr_frequency.attr,
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&dev_attr_srpd.attr,
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NULL,
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};
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static struct attribute_group dev_attr_group = {
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.attrs = dev_attrs,
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};
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static int brcmstb_memc_probe(struct platform_device *pdev)
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{
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const struct brcmstb_memc_data *memc_data;
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struct device *dev = &pdev->dev;
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struct brcmstb_memc *memc;
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int ret;
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memc = devm_kzalloc(dev, sizeof(*memc), GFP_KERNEL);
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if (!memc)
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return -ENOMEM;
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dev_set_drvdata(dev, memc);
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memc_data = device_get_match_data(dev);
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memc->srpd_offset = memc_data->srpd_offset;
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memc->ddr_ctrl = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(memc->ddr_ctrl))
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return PTR_ERR(memc->ddr_ctrl);
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of_property_read_u32(pdev->dev.of_node, "clock-frequency",
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&memc->frequency);
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ret = sysfs_create_group(&dev->kobj, &dev_attr_group);
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if (ret)
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return ret;
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return 0;
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}
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static void brcmstb_memc_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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sysfs_remove_group(&dev->kobj, &dev_attr_group);
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}
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enum brcmstb_memc_hwtype {
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BRCMSTB_MEMC_V21,
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BRCMSTB_MEMC_V20,
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BRCMSTB_MEMC_V1X,
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};
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static const struct brcmstb_memc_data brcmstb_memc_versions[] = {
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{ .srpd_offset = REG_MEMC_SRPD_CFG_21 },
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{ .srpd_offset = REG_MEMC_SRPD_CFG_20 },
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{ .srpd_offset = REG_MEMC_SRPD_CFG_1x },
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};
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static const struct of_device_id brcmstb_memc_of_match[] = {
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.1.x",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V1X]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.0",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V20]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.5",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.6",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.7",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.8",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.0",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.2",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.3",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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{
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.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.4",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
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},
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/* default to the original offset */
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{
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.compatible = "brcm,brcmstb-memc-ddr",
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.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V1X]
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},
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{}
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};
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static int brcmstb_memc_suspend(struct device *dev)
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{
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struct brcmstb_memc *memc = dev_get_drvdata(dev);
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void __iomem *cfg = memc->ddr_ctrl + memc->srpd_offset;
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u32 val;
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if (memc->timeout_cycles == 0)
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return 0;
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/*
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* Disable SRPD prior to suspending the system since that can
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* cause issues with other memory clients managed by the ARM
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* trusted firmware to access memory.
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*/
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val = readl_relaxed(cfg);
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val &= ~BIT(SRPD_EN_SHIFT);
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writel_relaxed(val, cfg);
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/* Ensure the write is committed to the controller */
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(void)readl_relaxed(cfg);
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return 0;
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}
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static int brcmstb_memc_resume(struct device *dev)
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{
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struct brcmstb_memc *memc = dev_get_drvdata(dev);
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if (memc->timeout_cycles == 0)
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return 0;
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return brcmstb_memc_srpd_config(memc, memc->timeout_cycles);
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}
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static DEFINE_SIMPLE_DEV_PM_OPS(brcmstb_memc_pm_ops, brcmstb_memc_suspend,
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brcmstb_memc_resume);
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static struct platform_driver brcmstb_memc_driver = {
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.probe = brcmstb_memc_probe,
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.remove_new = brcmstb_memc_remove,
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.driver = {
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.name = "brcmstb_memc",
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.of_match_table = brcmstb_memc_of_match,
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.pm = pm_ptr(&brcmstb_memc_pm_ops),
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},
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};
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module_platform_driver(brcmstb_memc_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Broadcom");
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MODULE_DESCRIPTION("DDR SRPD driver for Broadcom STB chips");
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