518 lines
13 KiB
C
518 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2023 Intel Corporation. All rights reserved. */
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#include <linux/acpi.h>
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#include <linux/xarray.h>
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#include <linux/fw_table.h>
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#include <linux/node.h>
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#include <linux/overflow.h>
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#include "cxlpci.h"
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#include "cxlmem.h"
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#include "core.h"
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#include "cxl.h"
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struct dsmas_entry {
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struct range dpa_range;
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u8 handle;
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struct access_coordinate coord;
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int entries;
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int qos_class;
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};
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static int cdat_dsmas_handler(union acpi_subtable_headers *header, void *arg,
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const unsigned long end)
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{
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struct acpi_cdat_header *hdr = &header->cdat;
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struct acpi_cdat_dsmas *dsmas;
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int size = sizeof(*hdr) + sizeof(*dsmas);
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struct xarray *dsmas_xa = arg;
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struct dsmas_entry *dent;
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u16 len;
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int rc;
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len = le16_to_cpu((__force __le16)hdr->length);
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if (len != size || (unsigned long)hdr + len > end) {
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pr_warn("Malformed DSMAS table length: (%u:%u)\n", size, len);
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return -EINVAL;
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}
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/* Skip common header */
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dsmas = (struct acpi_cdat_dsmas *)(hdr + 1);
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dent = kzalloc(sizeof(*dent), GFP_KERNEL);
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if (!dent)
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return -ENOMEM;
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dent->handle = dsmas->dsmad_handle;
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dent->dpa_range.start = le64_to_cpu((__force __le64)dsmas->dpa_base_address);
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dent->dpa_range.end = le64_to_cpu((__force __le64)dsmas->dpa_base_address) +
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le64_to_cpu((__force __le64)dsmas->dpa_length) - 1;
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rc = xa_insert(dsmas_xa, dent->handle, dent, GFP_KERNEL);
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if (rc) {
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kfree(dent);
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return rc;
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}
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return 0;
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}
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static void cxl_access_coordinate_set(struct access_coordinate *coord,
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int access, unsigned int val)
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{
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switch (access) {
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case ACPI_HMAT_ACCESS_LATENCY:
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coord->read_latency = val;
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coord->write_latency = val;
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break;
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case ACPI_HMAT_READ_LATENCY:
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coord->read_latency = val;
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break;
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case ACPI_HMAT_WRITE_LATENCY:
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coord->write_latency = val;
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break;
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case ACPI_HMAT_ACCESS_BANDWIDTH:
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coord->read_bandwidth = val;
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coord->write_bandwidth = val;
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break;
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case ACPI_HMAT_READ_BANDWIDTH:
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coord->read_bandwidth = val;
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break;
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case ACPI_HMAT_WRITE_BANDWIDTH:
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coord->write_bandwidth = val;
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break;
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}
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}
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static int cdat_dslbis_handler(union acpi_subtable_headers *header, void *arg,
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const unsigned long end)
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{
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struct acpi_cdat_header *hdr = &header->cdat;
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struct acpi_cdat_dslbis *dslbis;
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int size = sizeof(*hdr) + sizeof(*dslbis);
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struct xarray *dsmas_xa = arg;
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struct dsmas_entry *dent;
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__le64 le_base;
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__le16 le_val;
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u64 val;
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u16 len;
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int rc;
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len = le16_to_cpu((__force __le16)hdr->length);
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if (len != size || (unsigned long)hdr + len > end) {
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pr_warn("Malformed DSLBIS table length: (%u:%u)\n", size, len);
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return -EINVAL;
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}
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/* Skip common header */
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dslbis = (struct acpi_cdat_dslbis *)(hdr + 1);
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/* Skip unrecognized data type */
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if (dslbis->data_type > ACPI_HMAT_WRITE_BANDWIDTH)
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return 0;
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/* Not a memory type, skip */
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if ((dslbis->flags & ACPI_HMAT_MEMORY_HIERARCHY) != ACPI_HMAT_MEMORY)
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return 0;
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dent = xa_load(dsmas_xa, dslbis->handle);
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if (!dent) {
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pr_warn("No matching DSMAS entry for DSLBIS entry.\n");
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return 0;
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}
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le_base = (__force __le64)dslbis->entry_base_unit;
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le_val = (__force __le16)dslbis->entry[0];
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rc = check_mul_overflow(le64_to_cpu(le_base),
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le16_to_cpu(le_val), &val);
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if (rc)
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pr_warn("DSLBIS value overflowed.\n");
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cxl_access_coordinate_set(&dent->coord, dslbis->data_type, val);
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return 0;
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}
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static int cdat_table_parse_output(int rc)
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{
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if (rc < 0)
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return rc;
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if (rc == 0)
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return -ENOENT;
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return 0;
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}
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static int cxl_cdat_endpoint_process(struct cxl_port *port,
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struct xarray *dsmas_xa)
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{
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int rc;
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rc = cdat_table_parse(ACPI_CDAT_TYPE_DSMAS, cdat_dsmas_handler,
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dsmas_xa, port->cdat.table);
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rc = cdat_table_parse_output(rc);
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if (rc)
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return rc;
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rc = cdat_table_parse(ACPI_CDAT_TYPE_DSLBIS, cdat_dslbis_handler,
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dsmas_xa, port->cdat.table);
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return cdat_table_parse_output(rc);
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}
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static int cxl_port_perf_data_calculate(struct cxl_port *port,
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struct xarray *dsmas_xa)
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{
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struct access_coordinate ep_c;
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struct access_coordinate coord[ACCESS_COORDINATE_MAX];
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struct dsmas_entry *dent;
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int valid_entries = 0;
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unsigned long index;
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int rc;
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rc = cxl_endpoint_get_perf_coordinates(port, &ep_c);
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if (rc) {
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dev_dbg(&port->dev, "Failed to retrieve ep perf coordinates.\n");
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return rc;
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}
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rc = cxl_hb_get_perf_coordinates(port, coord);
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if (rc) {
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dev_dbg(&port->dev, "Failed to retrieve hb perf coordinates.\n");
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return rc;
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}
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struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port);
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if (!cxl_root)
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return -ENODEV;
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if (!cxl_root->ops || !cxl_root->ops->qos_class)
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return -EOPNOTSUPP;
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xa_for_each(dsmas_xa, index, dent) {
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int qos_class;
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cxl_coordinates_combine(&dent->coord, &dent->coord, &ep_c);
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/*
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* Keeping the host bridge coordinates separate from the dsmas
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* coordinates in order to allow calculation of access class
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* 0 and 1 for region later.
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*/
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cxl_coordinates_combine(&coord[ACCESS_COORDINATE_LOCAL],
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&coord[ACCESS_COORDINATE_LOCAL],
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&dent->coord);
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dent->entries = 1;
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rc = cxl_root->ops->qos_class(cxl_root,
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&coord[ACCESS_COORDINATE_LOCAL],
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1, &qos_class);
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if (rc != 1)
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continue;
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valid_entries++;
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dent->qos_class = qos_class;
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}
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if (!valid_entries)
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return -ENOENT;
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return 0;
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}
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static void update_perf_entry(struct device *dev, struct dsmas_entry *dent,
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struct cxl_dpa_perf *dpa_perf)
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{
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dpa_perf->dpa_range = dent->dpa_range;
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dpa_perf->coord = dent->coord;
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dpa_perf->qos_class = dent->qos_class;
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dev_dbg(dev,
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"DSMAS: dpa: %#llx qos: %d read_bw: %d write_bw %d read_lat: %d write_lat: %d\n",
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dent->dpa_range.start, dpa_perf->qos_class,
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dent->coord.read_bandwidth, dent->coord.write_bandwidth,
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dent->coord.read_latency, dent->coord.write_latency);
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}
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static void cxl_memdev_set_qos_class(struct cxl_dev_state *cxlds,
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struct xarray *dsmas_xa)
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{
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struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
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struct device *dev = cxlds->dev;
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struct range pmem_range = {
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.start = cxlds->pmem_res.start,
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.end = cxlds->pmem_res.end,
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};
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struct range ram_range = {
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.start = cxlds->ram_res.start,
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.end = cxlds->ram_res.end,
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};
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struct dsmas_entry *dent;
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unsigned long index;
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xa_for_each(dsmas_xa, index, dent) {
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if (resource_size(&cxlds->ram_res) &&
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range_contains(&ram_range, &dent->dpa_range))
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update_perf_entry(dev, dent, &mds->ram_perf);
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else if (resource_size(&cxlds->pmem_res) &&
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range_contains(&pmem_range, &dent->dpa_range))
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update_perf_entry(dev, dent, &mds->pmem_perf);
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else
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dev_dbg(dev, "no partition for dsmas dpa: %#llx\n",
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dent->dpa_range.start);
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}
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}
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static int match_cxlrd_qos_class(struct device *dev, void *data)
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{
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int dev_qos_class = *(int *)data;
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struct cxl_root_decoder *cxlrd;
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if (!is_root_decoder(dev))
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return 0;
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cxlrd = to_cxl_root_decoder(dev);
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if (cxlrd->qos_class == CXL_QOS_CLASS_INVALID)
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return 0;
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if (cxlrd->qos_class == dev_qos_class)
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return 1;
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return 0;
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}
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static void reset_dpa_perf(struct cxl_dpa_perf *dpa_perf)
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{
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*dpa_perf = (struct cxl_dpa_perf) {
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.qos_class = CXL_QOS_CLASS_INVALID,
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};
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}
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static bool cxl_qos_match(struct cxl_port *root_port,
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struct cxl_dpa_perf *dpa_perf)
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{
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if (dpa_perf->qos_class == CXL_QOS_CLASS_INVALID)
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return false;
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if (!device_for_each_child(&root_port->dev, &dpa_perf->qos_class,
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match_cxlrd_qos_class))
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return false;
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return true;
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}
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static int match_cxlrd_hb(struct device *dev, void *data)
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{
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struct device *host_bridge = data;
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struct cxl_switch_decoder *cxlsd;
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struct cxl_root_decoder *cxlrd;
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if (!is_root_decoder(dev))
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return 0;
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cxlrd = to_cxl_root_decoder(dev);
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cxlsd = &cxlrd->cxlsd;
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guard(rwsem_read)(&cxl_region_rwsem);
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for (int i = 0; i < cxlsd->nr_targets; i++) {
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if (host_bridge == cxlsd->target[i]->dport_dev)
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return 1;
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}
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return 0;
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}
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static int cxl_qos_class_verify(struct cxl_memdev *cxlmd)
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{
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
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struct cxl_port *root_port;
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int rc;
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struct cxl_root *cxl_root __free(put_cxl_root) =
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find_cxl_root(cxlmd->endpoint);
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if (!cxl_root)
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return -ENODEV;
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root_port = &cxl_root->port;
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/* Check that the QTG IDs are all sane between end device and root decoders */
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if (!cxl_qos_match(root_port, &mds->ram_perf))
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reset_dpa_perf(&mds->ram_perf);
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if (!cxl_qos_match(root_port, &mds->pmem_perf))
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reset_dpa_perf(&mds->pmem_perf);
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/* Check to make sure that the device's host bridge is under a root decoder */
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rc = device_for_each_child(&root_port->dev,
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cxlmd->endpoint->host_bridge, match_cxlrd_hb);
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if (!rc) {
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reset_dpa_perf(&mds->ram_perf);
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reset_dpa_perf(&mds->pmem_perf);
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}
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return rc;
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}
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static void discard_dsmas(struct xarray *xa)
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{
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unsigned long index;
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void *ent;
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xa_for_each(xa, index, ent) {
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xa_erase(xa, index);
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kfree(ent);
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}
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xa_destroy(xa);
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}
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DEFINE_FREE(dsmas, struct xarray *, if (_T) discard_dsmas(_T))
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void cxl_endpoint_parse_cdat(struct cxl_port *port)
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{
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||
|
|
struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
|
||
|
|
struct cxl_dev_state *cxlds = cxlmd->cxlds;
|
||
|
|
struct xarray __dsmas_xa;
|
||
|
|
struct xarray *dsmas_xa __free(dsmas) = &__dsmas_xa;
|
||
|
|
int rc;
|
||
|
|
|
||
|
|
xa_init(&__dsmas_xa);
|
||
|
|
if (!port->cdat.table)
|
||
|
|
return;
|
||
|
|
|
||
|
|
rc = cxl_cdat_endpoint_process(port, dsmas_xa);
|
||
|
|
if (rc < 0) {
|
||
|
|
dev_dbg(&port->dev, "Failed to parse CDAT: %d\n", rc);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
rc = cxl_port_perf_data_calculate(port, dsmas_xa);
|
||
|
|
if (rc) {
|
||
|
|
dev_dbg(&port->dev, "Failed to do perf coord calculations.\n");
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
cxl_memdev_set_qos_class(cxlds, dsmas_xa);
|
||
|
|
cxl_qos_class_verify(cxlmd);
|
||
|
|
cxl_memdev_update_perf(cxlmd);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_NS_GPL(cxl_endpoint_parse_cdat, CXL);
|
||
|
|
|
||
|
|
static int cdat_sslbis_handler(union acpi_subtable_headers *header, void *arg,
|
||
|
|
const unsigned long end)
|
||
|
|
{
|
||
|
|
struct acpi_cdat_sslbis_table {
|
||
|
|
struct acpi_cdat_header header;
|
||
|
|
struct acpi_cdat_sslbis sslbis_header;
|
||
|
|
struct acpi_cdat_sslbe entries[];
|
||
|
|
} *tbl = (struct acpi_cdat_sslbis_table *)header;
|
||
|
|
int size = sizeof(header->cdat) + sizeof(tbl->sslbis_header);
|
||
|
|
struct acpi_cdat_sslbis *sslbis;
|
||
|
|
struct cxl_port *port = arg;
|
||
|
|
struct device *dev = &port->dev;
|
||
|
|
int remain, entries, i;
|
||
|
|
u16 len;
|
||
|
|
|
||
|
|
len = le16_to_cpu((__force __le16)header->cdat.length);
|
||
|
|
remain = len - size;
|
||
|
|
if (!remain || remain % sizeof(tbl->entries[0]) ||
|
||
|
|
(unsigned long)header + len > end) {
|
||
|
|
dev_warn(dev, "Malformed SSLBIS table length: (%u)\n", len);
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
sslbis = &tbl->sslbis_header;
|
||
|
|
/* Unrecognized data type, we can skip */
|
||
|
|
if (sslbis->data_type > ACPI_HMAT_WRITE_BANDWIDTH)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
entries = remain / sizeof(tbl->entries[0]);
|
||
|
|
if (struct_size(tbl, entries, entries) != len)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
for (i = 0; i < entries; i++) {
|
||
|
|
u16 x = le16_to_cpu((__force __le16)tbl->entries[i].portx_id);
|
||
|
|
u16 y = le16_to_cpu((__force __le16)tbl->entries[i].porty_id);
|
||
|
|
__le64 le_base;
|
||
|
|
__le16 le_val;
|
||
|
|
struct cxl_dport *dport;
|
||
|
|
unsigned long index;
|
||
|
|
u16 dsp_id;
|
||
|
|
u64 val;
|
||
|
|
|
||
|
|
switch (x) {
|
||
|
|
case ACPI_CDAT_SSLBIS_US_PORT:
|
||
|
|
dsp_id = y;
|
||
|
|
break;
|
||
|
|
case ACPI_CDAT_SSLBIS_ANY_PORT:
|
||
|
|
switch (y) {
|
||
|
|
case ACPI_CDAT_SSLBIS_US_PORT:
|
||
|
|
dsp_id = x;
|
||
|
|
break;
|
||
|
|
case ACPI_CDAT_SSLBIS_ANY_PORT:
|
||
|
|
dsp_id = ACPI_CDAT_SSLBIS_ANY_PORT;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
dsp_id = y;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
dsp_id = x;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
le_base = (__force __le64)tbl->sslbis_header.entry_base_unit;
|
||
|
|
le_val = (__force __le16)tbl->entries[i].latency_or_bandwidth;
|
||
|
|
|
||
|
|
if (check_mul_overflow(le64_to_cpu(le_base),
|
||
|
|
le16_to_cpu(le_val), &val))
|
||
|
|
dev_warn(dev, "SSLBIS value overflowed!\n");
|
||
|
|
|
||
|
|
xa_for_each(&port->dports, index, dport) {
|
||
|
|
if (dsp_id == ACPI_CDAT_SSLBIS_ANY_PORT ||
|
||
|
|
dsp_id == dport->port_id)
|
||
|
|
cxl_access_coordinate_set(&dport->sw_coord,
|
||
|
|
sslbis->data_type,
|
||
|
|
val);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void cxl_switch_parse_cdat(struct cxl_port *port)
|
||
|
|
{
|
||
|
|
int rc;
|
||
|
|
|
||
|
|
if (!port->cdat.table)
|
||
|
|
return;
|
||
|
|
|
||
|
|
rc = cdat_table_parse(ACPI_CDAT_TYPE_SSLBIS, cdat_sslbis_handler,
|
||
|
|
port, port->cdat.table);
|
||
|
|
rc = cdat_table_parse_output(rc);
|
||
|
|
if (rc)
|
||
|
|
dev_dbg(&port->dev, "Failed to parse SSLBIS: %d\n", rc);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_NS_GPL(cxl_switch_parse_cdat, CXL);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* cxl_coordinates_combine - Combine the two input coordinates
|
||
|
|
*
|
||
|
|
* @out: Output coordinate of c1 and c2 combined
|
||
|
|
* @c1: input coordinates
|
||
|
|
* @c2: input coordinates
|
||
|
|
*/
|
||
|
|
void cxl_coordinates_combine(struct access_coordinate *out,
|
||
|
|
struct access_coordinate *c1,
|
||
|
|
struct access_coordinate *c2)
|
||
|
|
{
|
||
|
|
if (c1->write_bandwidth && c2->write_bandwidth)
|
||
|
|
out->write_bandwidth = min(c1->write_bandwidth,
|
||
|
|
c2->write_bandwidth);
|
||
|
|
out->write_latency = c1->write_latency + c2->write_latency;
|
||
|
|
|
||
|
|
if (c1->read_bandwidth && c2->read_bandwidth)
|
||
|
|
out->read_bandwidth = min(c1->read_bandwidth,
|
||
|
|
c2->read_bandwidth);
|
||
|
|
out->read_latency = c1->read_latency + c2->read_latency;
|
||
|
|
}
|
||
|
|
|
||
|
|
MODULE_IMPORT_NS(CXL);
|