430 lines
14 KiB
C
430 lines
14 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* include/asm-xtensa/pgtable.h
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*
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* Copyright (C) 2001 - 2013 Tensilica Inc.
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*/
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#ifndef _XTENSA_PGTABLE_H
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#define _XTENSA_PGTABLE_H
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#include <asm/page.h>
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#include <asm/kmem_layout.h>
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#include <asm-generic/pgtable-nopmd.h>
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/*
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* We only use two ring levels, user and kernel space.
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*/
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#ifdef CONFIG_MMU
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#define USER_RING 1 /* user ring level */
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#else
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#define USER_RING 0
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#endif
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#define KERNEL_RING 0 /* kernel ring level */
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/*
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* The Xtensa architecture port of Linux has a two-level page table system,
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* i.e. the logical three-level Linux page table layout is folded.
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* Each task has the following memory page tables:
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*
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* PGD table (page directory), ie. 3rd-level page table:
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* One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
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* (Architectures that don't have the PMD folded point to the PMD tables)
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*
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* The pointer to the PGD table for a given task can be retrieved from
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* the task structure (struct task_struct*) t, e.g. current():
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* (t->mm ? t->mm : t->active_mm)->pgd
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*
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* PMD tables (page middle-directory), ie. 2nd-level page tables:
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* Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
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*
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* PTE tables (page table entry), ie. 1st-level page tables:
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* One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
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* invalid_pte_table for absent mappings.
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*
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* The individual pages are 4 kB big with special pages for the empty_zero_page.
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*/
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#define PGDIR_SHIFT 22
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* Entries per page directory level: we use two-level, so
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* we don't really have any PMD directory physically.
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*/
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#define PTRS_PER_PTE 1024
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#define PTRS_PER_PTE_SHIFT 10
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#define PTRS_PER_PGD 1024
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#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
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#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
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#ifdef CONFIG_MMU
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/*
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* Virtual memory area. We keep a distance to other memory regions to be
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* on the safe side. We also use this area for cache aliasing.
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*/
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#define VMALLOC_START (XCHAL_KSEG_CACHED_VADDR - 0x10000000)
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#define VMALLOC_END (VMALLOC_START + 0x07FEFFFF)
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#define TLBTEMP_BASE_1 (VMALLOC_START + 0x08000000)
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#define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
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#if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
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#define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE)
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#else
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#define TLBTEMP_SIZE ICACHE_WAY_SIZE
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#endif
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#else
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#define VMALLOC_START __XTENSA_UL_CONST(0)
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#define VMALLOC_END __XTENSA_UL_CONST(0xffffffff)
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#endif
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/*
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* For the Xtensa architecture, the PTE layout is as follows:
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*
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* 31------12 11 10-9 8-6 5-4 3-2 1-0
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* +-----------------------------------------+
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* | | Software | HARDWARE |
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* | PPN | ADW | RI |Attribute|
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* +-----------------------------------------+
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* pte_none | MBZ | 01 | 11 | 00 |
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* +-----------------------------------------+
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* present | PPN | 0 | 00 | ADW | RI | CA | wx |
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* +- - - - - - - - - - - - - - - - - - - - -+
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* (PAGE_NONE)| PPN | 0 | 00 | ADW | 01 | 11 | 11 |
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* +-----------------------------------------+
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* swap | index | type | 01 | 11 | e0 |
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* +-----------------------------------------+
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*
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* For T1050 hardware and earlier the layout differs for present and (PAGE_NONE)
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* +-----------------------------------------+
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* present | PPN | 0 | 00 | ADW | RI | CA | w1 |
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* +-----------------------------------------+
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* (PAGE_NONE)| PPN | 0 | 00 | ADW | 01 | 01 | 00 |
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* +-----------------------------------------+
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*
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* Legend:
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* PPN Physical Page Number
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* ADW software: accessed (young) / dirty / writable
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* RI ring (0=privileged, 1=user, 2 and 3 are unused)
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* CA cache attribute: 00 bypass, 01 writeback, 10 writethrough
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* (11 is invalid and used to mark pages that are not present)
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* e exclusive marker in swap PTEs
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* w page is writable (hw)
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* x page is executable (hw)
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* index swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB)
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* (note that the index is always non-zero)
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* type swap type (5 bits -> 32 types)
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*
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* Notes:
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* - (PROT_NONE) is a special case of 'present' but causes an exception for
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* any access (read, write, and execute).
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* - 'multihit-exception' has the highest priority of all MMU exceptions,
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* so the ring must be set to 'RING_USER' even for 'non-present' pages.
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* - on older hardware, the exectuable flag was not supported and
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* used as a 'valid' flag, so it needs to be always set.
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* - we need to keep track of certain flags in software (dirty and young)
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* to do this, we use write exceptions and have a separate software w-flag.
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* - attribute value 1101 (and 1111 on T1050 and earlier) is reserved
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*/
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#define _PAGE_ATTRIB_MASK 0xf
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#define _PAGE_HW_EXEC (1<<0) /* hardware: page is executable */
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#define _PAGE_HW_WRITE (1<<1) /* hardware: page is writable */
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#define _PAGE_CA_BYPASS (0<<2) /* bypass, non-speculative */
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#define _PAGE_CA_WB (1<<2) /* write-back */
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#define _PAGE_CA_WT (2<<2) /* write-through */
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#define _PAGE_CA_MASK (3<<2)
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#define _PAGE_CA_INVALID (3<<2)
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/* We use invalid attribute values to distinguish special pte entries */
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#if XCHAL_HW_VERSION_MAJOR < 2000
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#define _PAGE_HW_VALID 0x01 /* older HW needed this bit set */
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#define _PAGE_NONE 0x04
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#else
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#define _PAGE_HW_VALID 0x00
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#define _PAGE_NONE 0x0f
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#endif
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#define _PAGE_USER (1<<4) /* user access (ring=1) */
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/* Software */
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#define _PAGE_WRITABLE_BIT 6
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#define _PAGE_WRITABLE (1<<6) /* software: page writable */
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#define _PAGE_DIRTY (1<<7) /* software: page dirty */
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#define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */
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/* We borrow bit 1 to store the exclusive marker in swap PTEs. */
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#define _PAGE_SWP_EXCLUSIVE (1<<1)
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#ifdef CONFIG_MMU
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#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
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#define _PAGE_PRESENT (_PAGE_HW_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)
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#define PAGE_NONE __pgprot(_PAGE_NONE | _PAGE_USER)
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#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER)
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#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
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#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER)
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#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
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#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
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#define PAGE_SHARED_EXEC \
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__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
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#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
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#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT)
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#define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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# define _PAGE_DIRECTORY (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_BYPASS)
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#else
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# define _PAGE_DIRECTORY (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
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#endif
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#else /* no mmu */
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# define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
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# define PAGE_NONE __pgprot(0)
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# define PAGE_SHARED __pgprot(0)
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# define PAGE_COPY __pgprot(0)
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# define PAGE_READONLY __pgprot(0)
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# define PAGE_KERNEL __pgprot(0)
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#endif
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/*
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* On certain configurations of Xtensa MMUs (eg. the initial Linux config),
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* the MMU can't do page protection for execute, and considers that the same as
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* read. Also, write permissions may imply read permissions.
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* What follows is the closest we can get by reasonable means..
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* See linux/mm/mmap.c for protection_map[] array that uses these definitions.
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*/
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#ifndef __ASSEMBLY__
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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extern unsigned long empty_zero_page[1024];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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#ifdef CONFIG_MMU
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extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
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extern void paging_init(void);
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#else
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# define swapper_pg_dir NULL
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static inline void paging_init(void) { }
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#endif
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/*
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* The pmd contains the kernel virtual address of the pte page.
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*/
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#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
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#define pmd_pfn(pmd) (__pa(pmd_val(pmd)) >> PAGE_SHIFT)
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#define pmd_page(pmd) virt_to_page(pmd_val(pmd))
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/*
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* pte status.
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*/
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# define pte_none(pte) (pte_val(pte) == (_PAGE_CA_INVALID | _PAGE_USER))
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#if XCHAL_HW_VERSION_MAJOR < 2000
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# define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)
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#else
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# define pte_present(pte) \
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(((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID) \
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|| ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE))
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#endif
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#define pte_clear(mm,addr,ptep) \
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do { update_pte(ptep, __pte(_PAGE_CA_INVALID | _PAGE_USER)); } while (0)
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#define pmd_none(pmd) (!pmd_val(pmd))
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#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
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#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
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#define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0)
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static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
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static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
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static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
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static inline pte_t pte_wrprotect(pte_t pte)
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{ pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; }
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static inline pte_t pte_mkclean(pte_t pte)
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{ pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; }
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static inline pte_t pte_mkold(pte_t pte)
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{ pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
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static inline pte_t pte_mkdirty(pte_t pte)
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{ pte_val(pte) |= _PAGE_DIRTY; return pte; }
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static inline pte_t pte_mkyoung(pte_t pte)
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{ pte_val(pte) |= _PAGE_ACCESSED; return pte; }
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static inline pte_t pte_mkwrite_novma(pte_t pte)
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{ pte_val(pte) |= _PAGE_WRITABLE; return pte; }
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#define pgprot_noncached(prot) \
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((__pgprot((pgprot_val(prot) & ~_PAGE_CA_MASK) | \
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_PAGE_CA_BYPASS)))
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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#define PFN_PTE_SHIFT PAGE_SHIFT
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#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
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#define pte_same(a,b) (pte_val(a) == pte_val(b))
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
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#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
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}
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/*
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* Certain architectures need to do special things when pte's
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* within a page table are directly modified. Thus, the following
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* hook is made available.
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*/
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static inline void update_pte(pte_t *ptep, pte_t pteval)
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{
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*ptep = pteval;
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#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
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__asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
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#endif
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}
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struct mm_struct;
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static inline void set_pte(pte_t *ptep, pte_t pte)
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{
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update_pte(ptep, pte);
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}
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static inline void
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set_pmd(pmd_t *pmdp, pmd_t pmdval)
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{
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*pmdp = pmdval;
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}
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struct vm_area_struct;
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static inline int
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ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
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pte_t *ptep)
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{
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pte_t pte = *ptep;
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if (!pte_young(pte))
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return 0;
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update_pte(ptep, pte_mkold(pte));
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline pte_t
|
||
|
|
ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
|
||
|
|
{
|
||
|
|
pte_t pte = *ptep;
|
||
|
|
pte_clear(mm, addr, ptep);
|
||
|
|
return pte;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void
|
||
|
|
ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
|
||
|
|
{
|
||
|
|
pte_t pte = *ptep;
|
||
|
|
update_pte(ptep, pte_wrprotect(pte));
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
|
||
|
|
* are !pte_none() && !pte_present().
|
||
|
|
*/
|
||
|
|
#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5)
|
||
|
|
|
||
|
|
#define __swp_type(entry) (((entry).val >> 6) & 0x1f)
|
||
|
|
#define __swp_offset(entry) ((entry).val >> 11)
|
||
|
|
#define __swp_entry(type,offs) \
|
||
|
|
((swp_entry_t){(((type) & 0x1f) << 6) | ((offs) << 11) | \
|
||
|
|
_PAGE_CA_INVALID | _PAGE_USER})
|
||
|
|
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
|
||
|
|
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
|
||
|
|
|
||
|
|
static inline int pte_swp_exclusive(pte_t pte)
|
||
|
|
{
|
||
|
|
return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline pte_t pte_swp_mkexclusive(pte_t pte)
|
||
|
|
{
|
||
|
|
pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
|
||
|
|
return pte;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline pte_t pte_swp_clear_exclusive(pte_t pte)
|
||
|
|
{
|
||
|
|
pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
|
||
|
|
return pte;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* !defined (__ASSEMBLY__) */
|
||
|
|
|
||
|
|
|
||
|
|
#ifdef __ASSEMBLY__
|
||
|
|
|
||
|
|
/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
|
||
|
|
* _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
|
||
|
|
* _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
|
||
|
|
* _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
|
||
|
|
*
|
||
|
|
* Note: We require an additional temporary register which can be the same as
|
||
|
|
* the register that holds the address.
|
||
|
|
*
|
||
|
|
* ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
#define _PGD_INDEX(rt,rs) extui rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
|
||
|
|
#define _PTE_INDEX(rt,rs) extui rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
|
||
|
|
|
||
|
|
#define _PGD_OFFSET(mm,adr,tmp) l32i mm, mm, MM_PGD; \
|
||
|
|
_PGD_INDEX(tmp, adr); \
|
||
|
|
addx4 mm, tmp, mm
|
||
|
|
|
||
|
|
#define _PTE_OFFSET(pmd,adr,tmp) _PTE_INDEX(tmp, adr); \
|
||
|
|
srli pmd, pmd, PAGE_SHIFT; \
|
||
|
|
slli pmd, pmd, PAGE_SHIFT; \
|
||
|
|
addx4 pmd, tmp, pmd
|
||
|
|
|
||
|
|
#else
|
||
|
|
|
||
|
|
struct vm_fault;
|
||
|
|
void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
|
||
|
|
unsigned long address, pte_t *ptep, unsigned int nr);
|
||
|
|
#define update_mmu_cache(vma, address, ptep) \
|
||
|
|
update_mmu_cache_range(NULL, vma, address, ptep, 1)
|
||
|
|
|
||
|
|
typedef pte_t *pte_addr_t;
|
||
|
|
|
||
|
|
void update_mmu_tlb(struct vm_area_struct *vma,
|
||
|
|
unsigned long address, pte_t *ptep);
|
||
|
|
#define __HAVE_ARCH_UPDATE_MMU_TLB
|
||
|
|
|
||
|
|
#endif /* !defined (__ASSEMBLY__) */
|
||
|
|
|
||
|
|
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
|
||
|
|
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
|
||
|
|
#define __HAVE_ARCH_PTEP_SET_WRPROTECT
|
||
|
|
#define __HAVE_ARCH_PTEP_MKDIRTY
|
||
|
|
#define __HAVE_ARCH_PTE_SAME
|
||
|
|
/* We provide our own get_unmapped_area to cope with
|
||
|
|
* SHM area cache aliasing for userland.
|
||
|
|
*/
|
||
|
|
#define HAVE_ARCH_UNMAPPED_AREA
|
||
|
|
|
||
|
|
#endif /* _XTENSA_PGTABLE_H */
|