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mirror_ubuntu-kernels/arch/riscv/boot/dts/starfive/jh7110.dtsi

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lowlatency-hwe-6.8-next
2024-07-02 00:48:40 +03:00
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
*/
/dts-v1/;
#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include <dt-bindings/power/starfive,jh7110-pmu.h>
#include <dt-bindings/reset/starfive,jh7110-crg.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "starfive,jh7110";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
S7_0: cpu@0 {
compatible = "sifive,s7", "riscv";
reg = <0>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
next-level-cache = <&ccache>;
riscv,isa = "rv64imac_zba_zbb";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
"zifencei", "zihpm";
status = "disabled";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
U74_1: cpu@1 {
compatible = "sifive,u74-mc", "riscv";
reg = <1>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <40>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
"zicsr", "zifencei", "zihpm";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
#cooling-cells = <2>;
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
U74_2: cpu@2 {
compatible = "sifive,u74-mc", "riscv";
reg = <2>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <40>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
"zicsr", "zifencei", "zihpm";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
#cooling-cells = <2>;
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
U74_3: cpu@3 {
compatible = "sifive,u74-mc", "riscv";
reg = <3>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <40>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
"zicsr", "zifencei", "zihpm";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
#cooling-cells = <2>;
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
U74_4: cpu@4 {
compatible = "sifive,u74-mc", "riscv";
reg = <4>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <40>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
"zicsr", "zifencei", "zihpm";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
#cooling-cells = <2>;
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&S7_0>;
};
core1 {
cpu = <&U74_1>;
};
core2 {
cpu = <&U74_2>;
};
core3 {
cpu = <&U74_3>;
};
core4 {
cpu = <&U74_4>;
};
};
};
};
cpu_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-375000000 {
opp-hz = /bits/ 64 <375000000>;
opp-microvolt = <800000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <800000>;
};
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
opp-microvolt = <800000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1040000>;
};
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <15000>;
thermal-sensors = <&sfctemp>;
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&U74_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&U74_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&U74_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&U74_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
cpu_alert0: cpu-alert0 {
/* milliCelsius */
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu-crit {
/* milliCelsius */
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
dvp_clk: dvp-clock {
compatible = "fixed-clock";
clock-output-names = "dvp_clk";
#clock-cells = <0>;
};
gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
compatible = "fixed-clock";
clock-output-names = "gmac0_rgmii_rxin";
#clock-cells = <0>;
};
gmac0_rmii_refin: gmac0-rmii-refin-clock {
compatible = "fixed-clock";
clock-output-names = "gmac0_rmii_refin";
#clock-cells = <0>;
};
gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
compatible = "fixed-clock";
clock-output-names = "gmac1_rgmii_rxin";
#clock-cells = <0>;
};
gmac1_rmii_refin: gmac1-rmii-refin-clock {
compatible = "fixed-clock";
clock-output-names = "gmac1_rmii_refin";
#clock-cells = <0>;
};
hdmitx0_pixelclk: hdmitx0-pixel-clock {
compatible = "fixed-clock";
clock-output-names = "hdmitx0_pixelclk";
#clock-cells = <0>;
};
i2srx_bclk_ext: i2srx-bclk-ext-clock {
compatible = "fixed-clock";
clock-output-names = "i2srx_bclk_ext";
#clock-cells = <0>;
};
i2srx_lrck_ext: i2srx-lrck-ext-clock {
compatible = "fixed-clock";
clock-output-names = "i2srx_lrck_ext";
#clock-cells = <0>;
};
i2stx_bclk_ext: i2stx-bclk-ext-clock {
compatible = "fixed-clock";
clock-output-names = "i2stx_bclk_ext";
#clock-cells = <0>;
};
i2stx_lrck_ext: i2stx-lrck-ext-clock {
compatible = "fixed-clock";
clock-output-names = "i2stx_lrck_ext";
#clock-cells = <0>;
};
mclk_ext: mclk-ext-clock {
compatible = "fixed-clock";
clock-output-names = "mclk_ext";
#clock-cells = <0>;
};
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc";
#clock-cells = <0>;
};
rtc_osc: rtc-oscillator {
compatible = "fixed-clock";
clock-output-names = "rtc_osc";
#clock-cells = <0>;
};
stmmac_axi_setup: stmmac-axi-config {
snps,lpi_en;
snps,wr_osr_lmt = <15>;
snps,rd_osr_lmt = <15>;
snps,blen = <256 128 64 32 0 0 0>;
};
tdm_ext: tdm-ext-clock {
compatible = "fixed-clock";
clock-output-names = "tdm_ext";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clint: timer@2000000 {
compatible = "starfive,jh7110-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>,
<&cpu2_intc 3>, <&cpu2_intc 7>,
<&cpu3_intc 3>, <&cpu3_intc 7>,
<&cpu4_intc 3>, <&cpu4_intc 7>;
};
ccache: cache-controller@2010000 {
compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
reg = <0x0 0x2010000 0x0 0x4000>;
interrupts = <1>, <3>, <4>, <2>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <2048>;
cache-size = <2097152>;
cache-unified;
};
plic: interrupt-controller@c000000 {
compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
interrupts-extended = <&cpu0_intc 11>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>,
<&cpu4_intc 11>, <&cpu4_intc 9>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <0>;
riscv,ndev = <136>;
};
uart0: serial@10000000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x10000000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
<&syscrg JH7110_SYSCLK_UART0_APB>;
clock-names = "baudclk", "apb_pclk";
resets = <&syscrg JH7110_SYSRST_UART0_APB>;
interrupts = <32>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart1: serial@10010000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x10010000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
<&syscrg JH7110_SYSCLK_UART1_APB>;
clock-names = "baudclk", "apb_pclk";
resets = <&syscrg JH7110_SYSRST_UART1_APB>;
interrupts = <33>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart2: serial@10020000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x10020000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
<&syscrg JH7110_SYSCLK_UART2_APB>;
clock-names = "baudclk", "apb_pclk";
resets = <&syscrg JH7110_SYSRST_UART2_APB>;
interrupts = <34>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
i2c0: i2c@10030000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x10030000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
clock-names = "ref";
resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
interrupts = <35>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@10040000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x10040000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
clock-names = "ref";
resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
interrupts = <36>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@10050000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x10050000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
clock-names = "ref";
resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
interrupts = <37>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@10060000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x10060000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>,
<&syscrg JH7110_SYSCLK_SPI0_APB>;
clock-names = "sspclk", "apb_pclk";
resets = <&syscrg JH7110_SYSRST_SPI0_APB>;
interrupts = <38>;
arm,primecell-periphid = <0x00041022>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@10070000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x10070000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>,
<&syscrg JH7110_SYSCLK_SPI1_APB>;
clock-names = "sspclk", "apb_pclk";
resets = <&syscrg JH7110_SYSRST_SPI1_APB>;
interrupts = <39>;
arm,primecell-periphid = <0x00041022>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@10080000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x10080000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>,
<&syscrg JH7110_SYSCLK_SPI2_APB>;
clock-names = "sspclk", "apb_pclk";
resets = <&syscrg JH7110_SYSRST_SPI2_APB>;
interrupts = <40>;
arm,primecell-periphid = <0x00041022>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
tdm: tdm@10090000 {
compatible = "starfive,jh7110-tdm";
reg = <0x0 0x10090000 0x0 0x1000>;
clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>,
<&syscrg JH7110_SYSCLK_TDM_APB>,
<&syscrg JH7110_SYSCLK_TDM_INTERNAL>,
<&syscrg JH7110_SYSCLK_TDM_TDM>,
<&syscrg JH7110_SYSCLK_MCLK_INNER>,
<&tdm_ext>;
clock-names = "tdm_ahb", "tdm_apb",
"tdm_internal", "tdm",
"mclk_inner", "tdm_ext";
resets = <&syscrg JH7110_SYSRST_TDM_AHB>,
<&syscrg JH7110_SYSRST_TDM_APB>,
<&syscrg JH7110_SYSRST_TDM_CORE>;
dmas = <&dma 20>, <&dma 21>;
dma-names = "rx","tx";
#sound-dai-cells = <0>;
status = "disabled";
};
i2srx: i2s@100e0000 {
compatible = "starfive,jh7110-i2srx";
reg = <0x0 0x100e0000 0x0 0x1000>;
clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,
<&syscrg JH7110_SYSCLK_I2SRX_APB>,
<&syscrg JH7110_SYSCLK_MCLK>,
<&syscrg JH7110_SYSCLK_MCLK_INNER>,
<&mclk_ext>,
<&syscrg JH7110_SYSCLK_I2SRX_BCLK>,
<&syscrg JH7110_SYSCLK_I2SRX_LRCK>,
<&i2srx_bclk_ext>,
<&i2srx_lrck_ext>;
clock-names = "i2sclk", "apb", "mclk",
"mclk_inner", "mclk_ext", "bclk",
"lrck", "bclk_ext", "lrck_ext";
resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,
<&syscrg JH7110_SYSRST_I2SRX_BCLK>;
dmas = <0>, <&dma 24>;
dma-names = "tx", "rx";
starfive,syscon = <&sys_syscon 0x18 0x2>;
#sound-dai-cells = <0>;
status = "disabled";
};
pwmdac: pwmdac@100b0000 {
compatible = "starfive,jh7110-pwmdac";
reg = <0x0 0x100b0000 0x0 0x1000>;
clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>,
<&syscrg JH7110_SYSCLK_PWMDAC_CORE>;
clock-names = "apb", "core";
resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>;
dmas = <&dma 22>;
dma-names = "tx";
#sound-dai-cells = <0>;
status = "disabled";
};
usb0: usb@10100000 {
compatible = "starfive,jh7110-usb";
ranges = <0x0 0x0 0x10100000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
starfive,stg-syscon = <&stg_syscon 0x4>;
clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
<&stgcrg JH7110_STGCLK_USB0_STB>,
<&stgcrg JH7110_STGCLK_USB0_APB>,
<&stgcrg JH7110_STGCLK_USB0_AXI>,
<&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
<&stgcrg JH7110_STGRST_USB0_APB>,
<&stgcrg JH7110_STGRST_USB0_AXI>,
<&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
reset-names = "pwrup", "apb", "axi", "utmi_apb";
status = "disabled";
usb_cdns3: usb@0 {
compatible = "cdns,usb3";
reg = <0x0 0x10000>,
<0x10000 0x10000>,
<0x20000 0x10000>;
reg-names = "otg", "xhci", "dev";
interrupts = <100>, <108>, <110>;
interrupt-names = "host", "peripheral", "otg";
phys = <&usbphy0>;
phy-names = "cdns3,usb2-phy";
};
};
usbphy0: phy@10200000 {
compatible = "starfive,jh7110-usb-phy";
reg = <0x0 0x10200000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
<&stgcrg JH7110_STGCLK_USB0_APP_125>;
clock-names = "125m", "app_125m";
#phy-cells = <0>;
};
pciephy0: phy@10210000 {
compatible = "starfive,jh7110-pcie-phy";
reg = <0x0 0x10210000 0x0 0x10000>;
#phy-cells = <0>;
};
pciephy1: phy@10220000 {
compatible = "starfive,jh7110-pcie-phy";
reg = <0x0 0x10220000 0x0 0x10000>;
#phy-cells = <0>;
};
stgcrg: clock-controller@10230000 {
compatible = "starfive,jh7110-stgcrg";
reg = <0x0 0x10230000 0x0 0x10000>;
clocks = <&osc>,
<&syscrg JH7110_SYSCLK_HIFI4_CORE>,
<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
<&syscrg JH7110_SYSCLK_USB_125M>,
<&syscrg JH7110_SYSCLK_CPU_BUS>,
<&syscrg JH7110_SYSCLK_HIFI4_AXI>,
<&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
<&syscrg JH7110_SYSCLK_APB_BUS>;
clock-names = "osc", "hifi4_core",
"stg_axiahb", "usb_125m",
"cpu_bus", "hifi4_axi",
"nocstg_bus", "apb_bus";
#clock-cells = <1>;
#reset-cells = <1>;
};
stg_syscon: syscon@10240000 {
compatible = "starfive,jh7110-stg-syscon", "syscon";
reg = <0x0 0x10240000 0x0 0x1000>;
};
uart3: serial@12000000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x12000000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
<&syscrg JH7110_SYSCLK_UART3_APB>;
clock-names = "baudclk", "apb_pclk";
resets = <&syscrg JH7110_SYSRST_UART3_APB>;
interrupts = <45>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart4: serial@12010000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x12010000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
<&syscrg JH7110_SYSCLK_UART4_APB>;
clock-names = "baudclk", "apb_pclk";
resets = <&syscrg JH7110_SYSRST_UART4_APB>;
interrupts = <46>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart5: serial@12020000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x12020000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
<&syscrg JH7110_SYSCLK_UART5_APB>;
clock-names = "baudclk", "apb_pclk";
resets = <&syscrg JH7110_SYSRST_UART5_APB>;
interrupts = <47>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
i2c3: i2c@12030000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x12030000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
clock-names = "ref";
resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
interrupts = <48>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@12040000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x12040000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
clock-names = "ref";
resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
interrupts = <49>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@12050000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x12050000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
clock-names = "ref";
resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
interrupts = <50>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@12060000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x12060000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
clock-names = "ref";
resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
interrupts = <51>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi3: spi@12070000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x12070000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>,
<&syscrg JH7110_SYSCLK_SPI3_APB>;
clock-names = "sspclk", "apb_pclk";
resets = <&syscrg JH7110_SYSRST_SPI3_APB>;
interrupts = <52>;
arm,primecell-periphid = <0x00041022>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi4: spi@12080000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x12080000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>,
<&syscrg JH7110_SYSCLK_SPI4_APB>;
clock-names = "sspclk", "apb_pclk";
resets = <&syscrg JH7110_SYSRST_SPI4_APB>;
interrupts = <53>;
arm,primecell-periphid = <0x00041022>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi5: spi@12090000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x12090000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>,
<&syscrg JH7110_SYSCLK_SPI5_APB>;
clock-names = "sspclk", "apb_pclk";
resets = <&syscrg JH7110_SYSRST_SPI5_APB>;
interrupts = <54>;
arm,primecell-periphid = <0x00041022>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi6: spi@120a0000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x120A0000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>,
<&syscrg JH7110_SYSCLK_SPI6_APB>;
clock-names = "sspclk", "apb_pclk";
resets = <&syscrg JH7110_SYSRST_SPI6_APB>;
interrupts = <55>;
arm,primecell-periphid = <0x00041022>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2stx0: i2s@120b0000 {
compatible = "starfive,jh7110-i2stx0";
reg = <0x0 0x120b0000 0x0 0x1000>;
clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,
<&syscrg JH7110_SYSCLK_I2STX0_APB>,
<&syscrg JH7110_SYSCLK_MCLK>,
<&syscrg JH7110_SYSCLK_MCLK_INNER>,
<&mclk_ext>;
clock-names = "i2sclk", "apb", "mclk",
"mclk_inner","mclk_ext";
resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,
<&syscrg JH7110_SYSRST_I2STX0_BCLK>;
dmas = <&dma 47>;
dma-names = "tx";
#sound-dai-cells = <0>;
status = "disabled";
};
i2stx1: i2s@120c0000 {
compatible = "starfive,jh7110-i2stx1";
reg = <0x0 0x120c0000 0x0 0x1000>;
clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>,
<&syscrg JH7110_SYSCLK_I2STX1_APB>,
<&syscrg JH7110_SYSCLK_MCLK>,
<&syscrg JH7110_SYSCLK_MCLK_INNER>,
<&mclk_ext>,
<&syscrg JH7110_SYSCLK_I2STX1_BCLK>,
<&syscrg JH7110_SYSCLK_I2STX1_LRCK>,
<&i2stx_bclk_ext>,
<&i2stx_lrck_ext>;
clock-names = "i2sclk", "apb", "mclk",
"mclk_inner", "mclk_ext", "bclk",
"lrck", "bclk_ext", "lrck_ext";
resets = <&syscrg JH7110_SYSRST_I2STX1_APB>,
<&syscrg JH7110_SYSRST_I2STX1_BCLK>;
dmas = <&dma 48>;
dma-names = "tx";
#sound-dai-cells = <0>;
status = "disabled";
};
sfctemp: temperature-sensor@120e0000 {
compatible = "starfive,jh7110-temp";
reg = <0x0 0x120e0000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
<&syscrg JH7110_SYSCLK_TEMP_APB>;
clock-names = "sense", "bus";
resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
<&syscrg JH7110_SYSRST_TEMP_APB>;
reset-names = "sense", "bus";
#thermal-sensor-cells = <0>;
};
qspi: spi@13010000 {
compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
reg = <0x0 0x13010000 0x0 0x10000>,
<0x0 0x21000000 0x0 0x400000>;
interrupts = <25>;
clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
<&syscrg JH7110_SYSCLK_QSPI_AHB>,
<&syscrg JH7110_SYSCLK_QSPI_APB>;
clock-names = "ref", "ahb", "apb";
resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
<&syscrg JH7110_SYSRST_QSPI_AHB>,
<&syscrg JH7110_SYSRST_QSPI_REF>;
reset-names = "qspi", "qspi-ocp", "rstc_ref";
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
status = "disabled";
};
syscrg: clock-controller@13020000 {
compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;
clocks = <&osc>, <&gmac1_rmii_refin>,
<&gmac1_rgmii_rxin>,
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
<&tdm_ext>, <&mclk_ext>,
<&pllclk JH7110_PLLCLK_PLL0_OUT>,
<&pllclk JH7110_PLLCLK_PLL1_OUT>,
<&pllclk JH7110_PLLCLK_PLL2_OUT>;
clock-names = "osc", "gmac1_rmii_refin",
"gmac1_rgmii_rxin",
"i2stx_bclk_ext", "i2stx_lrck_ext",
"i2srx_bclk_ext", "i2srx_lrck_ext",
"tdm_ext", "mclk_ext",
"pll0_out", "pll1_out", "pll2_out";
#clock-cells = <1>;
#reset-cells = <1>;
};
sys_syscon: syscon@13030000 {
compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
reg = <0x0 0x13030000 0x0 0x1000>;
pllclk: clock-controller {
compatible = "starfive,jh7110-pll";
clocks = <&osc>;
#clock-cells = <1>;
};
};
sysgpio: pinctrl@13040000 {
compatible = "starfive,jh7110-sys-pinctrl";
reg = <0x0 0x13040000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
interrupts = <86>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
watchdog@13070000 {
compatible = "starfive,jh7110-wdt";
reg = <0x0 0x13070000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
<&syscrg JH7110_SYSCLK_WDT_CORE>;
clock-names = "apb", "core";
resets = <&syscrg JH7110_SYSRST_WDT_APB>,
<&syscrg JH7110_SYSRST_WDT_CORE>;
};
crypto: crypto@16000000 {
compatible = "starfive,jh7110-crypto";
reg = <0x0 0x16000000 0x0 0x4000>;
clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
<&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
clock-names = "hclk", "ahb";
interrupts = <28>;
resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
dmas = <&sdma 1 2>, <&sdma 0 2>;
dma-names = "tx", "rx";
};
sdma: dma-controller@16008000 {
compatible = "arm,pl080", "arm,primecell";
arm,primecell-periphid = <0x00041080>;
reg = <0x0 0x16008000 0x0 0x4000>;
interrupts = <29>;
clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>;
clock-names = "apb_pclk";
resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
lli-bus-interface-ahb1;
mem-bus-interface-ahb1;
memcpy-burst-size = <256>;
memcpy-bus-width = <32>;
#dma-cells = <2>;
};
rng: rng@1600c000 {
compatible = "starfive,jh7110-trng";
reg = <0x0 0x1600C000 0x0 0x4000>;
clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
<&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
clock-names = "hclk", "ahb";
resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
interrupts = <30>;
};
mmc0: mmc@16010000 {
compatible = "starfive,jh7110-mmc";
reg = <0x0 0x16010000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
<&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
clock-names = "biu","ciu";
resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
reset-names = "reset";
interrupts = <74>;
fifo-depth = <32>;
fifo-watermark-aligned;
data-addr = <0>;
starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
status = "disabled";
};
mmc1: mmc@16020000 {
compatible = "starfive,jh7110-mmc";
reg = <0x0 0x16020000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
<&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
clock-names = "biu","ciu";
resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
reset-names = "reset";
interrupts = <75>;
fifo-depth = <32>;
fifo-watermark-aligned;
data-addr = <0>;
starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
status = "disabled";
};
gmac0: ethernet@16030000 {
compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
reg = <0x0 0x16030000 0x0 0x10000>;
clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
<&aoncrg JH7110_AONCLK_GMAC0_AHB>,
<&syscrg JH7110_SYSCLK_GMAC0_PTP>,
<&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
<&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
clock-names = "stmmaceth", "pclk", "ptp_ref",
"tx", "gtx";
resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
<&aoncrg JH7110_AONRST_GMAC0_AHB>;
reset-names = "stmmaceth", "ahb";
interrupts = <7>, <6>, <5>;
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
rx-fifo-depth = <2048>;
tx-fifo-depth = <2048>;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <256>;
snps,fixed-burst;
snps,no-pbl-x8;
snps,force_thresh_dma_mode;
snps,axi-config = <&stmmac_axi_setup>;
snps,tso;
snps,en-tx-lpi-clockgating;
snps,txpbl = <16>;
snps,rxpbl = <16>;
starfive,syscon = <&aon_syscon 0xc 0x12>;
status = "disabled";
};
gmac1: ethernet@16040000 {
compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
reg = <0x0 0x16040000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
<&syscrg JH7110_SYSCLK_GMAC1_AHB>,
<&syscrg JH7110_SYSCLK_GMAC1_PTP>,
<&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
<&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
clock-names = "stmmaceth", "pclk", "ptp_ref",
"tx", "gtx";
resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
<&syscrg JH7110_SYSRST_GMAC1_AHB>;
reset-names = "stmmaceth", "ahb";
interrupts = <78>, <77>, <76>;
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
rx-fifo-depth = <2048>;
tx-fifo-depth = <2048>;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <256>;
snps,fixed-burst;
snps,no-pbl-x8;
snps,force_thresh_dma_mode;
snps,axi-config = <&stmmac_axi_setup>;
snps,tso;
snps,en-tx-lpi-clockgating;
snps,txpbl = <16>;
snps,rxpbl = <16>;
starfive,syscon = <&sys_syscon 0x90 0x2>;
status = "disabled";
};
dma: dma-controller@16050000 {
compatible = "starfive,jh7110-axi-dma";
reg = <0x0 0x16050000 0x0 0x10000>;
clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
<&stgcrg JH7110_STGCLK_DMA1P_AHB>;
clock-names = "core-clk", "cfgr-clk";
resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
<&stgcrg JH7110_STGRST_DMA1P_AHB>;
interrupts = <73>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <3>;
snps,block-size = <65536 65536 65536 65536>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <16>;
};
aoncrg: clock-controller@17000000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
clocks = <&osc>, <&gmac0_rmii_refin>,
<&gmac0_rgmii_rxin>,
<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
<&syscrg JH7110_SYSCLK_APB_BUS>,
<&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
<&rtc_osc>;
clock-names = "osc", "gmac0_rmii_refin",
"gmac0_rgmii_rxin", "stg_axiahb",
"apb_bus", "gmac0_gtxclk",
"rtc_osc";
#clock-cells = <1>;
#reset-cells = <1>;
};
aon_syscon: syscon@17010000 {
compatible = "starfive,jh7110-aon-syscon", "syscon";
reg = <0x0 0x17010000 0x0 0x1000>;
#power-domain-cells = <1>;
};
aongpio: pinctrl@17020000 {
compatible = "starfive,jh7110-aon-pinctrl";
reg = <0x0 0x17020000 0x0 0x10000>;
resets = <&aoncrg JH7110_AONRST_IOMUX>;
interrupts = <85>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
pwrc: power-controller@17030000 {
compatible = "starfive,jh7110-pmu";
reg = <0x0 0x17030000 0x0 0x10000>;
interrupts = <111>;
#power-domain-cells = <1>;
};
ispcrg: clock-controller@19810000 {
compatible = "starfive,jh7110-ispcrg";
reg = <0x0 0x19810000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
<&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
<&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
<&dvp_clk>;
clock-names = "isp_top_core", "isp_top_axi",
"noc_bus_isp_axi", "dvp_clk";
resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
<&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
<&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
#clock-cells = <1>;
#reset-cells = <1>;
power-domains = <&pwrc JH7110_PD_ISP>;
};
voutcrg: clock-controller@295c0000 {
compatible = "starfive,jh7110-voutcrg";
reg = <0x0 0x295c0000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
<&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
<&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
<&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
<&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
<&hdmitx0_pixelclk>;
clock-names = "vout_src", "vout_top_ahb",
"vout_top_axi", "vout_top_hdmitx0_mclk",
"i2stx0_bclk", "hdmitx0_pixelclk";
resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
power-domains = <&pwrc JH7110_PD_VOUT>;
};
};
};
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