78 lines
1.8 KiB
C
78 lines
1.8 KiB
C
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/*
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* Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
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* Copyright (C) 2009 Wind River Systems Inc
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* Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
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*
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* Based on DMA code from MIPS.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/string.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/cache.h>
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#include <asm/cacheflush.h>
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void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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void *vaddr = phys_to_virt(paddr);
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switch (dir) {
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case DMA_FROM_DEVICE:
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invalidate_dcache_range((unsigned long)vaddr,
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(unsigned long)(vaddr + size));
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break;
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case DMA_TO_DEVICE:
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/*
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* We just need to flush the caches here , but Nios2 flush
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* instruction will do both writeback and invalidate.
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*/
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case DMA_BIDIRECTIONAL: /* flush and invalidate */
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flush_dcache_range((unsigned long)vaddr,
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(unsigned long)(vaddr + size));
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break;
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default:
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BUG();
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}
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}
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void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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void *vaddr = phys_to_virt(paddr);
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switch (dir) {
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case DMA_BIDIRECTIONAL:
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case DMA_FROM_DEVICE:
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invalidate_dcache_range((unsigned long)vaddr,
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(unsigned long)(vaddr + size));
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break;
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case DMA_TO_DEVICE:
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break;
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default:
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BUG();
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}
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}
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void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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unsigned long start = (unsigned long)page_address(page);
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flush_dcache_range(start, start + size);
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}
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void *arch_dma_set_uncached(void *ptr, size_t size)
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{
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unsigned long addr = (unsigned long)ptr;
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addr |= CONFIG_NIOS2_IO_REGION_BASE;
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return (void *)ptr;
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}
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