102 lines
2.0 KiB
Plaintext
102 lines
2.0 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/**
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* DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
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* J7200 board.
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*
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include "k3-pinctrl.h"
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#include "k3-serdes.h"
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&{/} {
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aliases {
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ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
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ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
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ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
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ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
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};
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};
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&cpsw0 {
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status = "okay";
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};
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&cpsw0_port1 {
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status = "okay";
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phy-handle = <&cpsw5g_phy0>;
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phy-mode = "qsgmii";
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mac-address = [00 00 00 00 00 00];
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phys = <&cpsw0_phy_gmii_sel 1>;
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};
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&cpsw0_port2 {
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status = "okay";
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phy-handle = <&cpsw5g_phy1>;
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phy-mode = "qsgmii";
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mac-address = [00 00 00 00 00 00];
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phys = <&cpsw0_phy_gmii_sel 2>;
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};
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&cpsw0_port3 {
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status = "okay";
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phy-handle = <&cpsw5g_phy2>;
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phy-mode = "qsgmii";
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mac-address = [00 00 00 00 00 00];
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phys = <&cpsw0_phy_gmii_sel 3>;
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};
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&cpsw0_port4 {
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status = "okay";
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phy-handle = <&cpsw5g_phy3>;
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phy-mode = "qsgmii";
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mac-address = [00 00 00 00 00 00];
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phys = <&cpsw0_phy_gmii_sel 4>;
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};
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&cpsw5g_mdio {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mdio0_pins_default>;
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reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
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reset-post-delay-us = <120000>;
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#address-cells = <1>;
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#size-cells = <0>;
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cpsw5g_phy0: ethernet-phy@16 {
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reg = <16>;
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};
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cpsw5g_phy1: ethernet-phy@17 {
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reg = <17>;
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};
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cpsw5g_phy2: ethernet-phy@18 {
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reg = <18>;
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};
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cpsw5g_phy3: ethernet-phy@19 {
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reg = <19>;
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};
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};
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&exp2 {
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qsgmii-line-hog {
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gpio-hog;
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gpios = <16 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "qsgmii-pwrdn-line";
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};
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};
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&main_pmx0 {
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mdio0_pins_default: mdio0-default-pins {
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pinctrl-single,pins = <
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J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */
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J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */
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>;
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};
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};
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