60 lines
1.4 KiB
Plaintext
60 lines
1.4 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2022 Arm Ltd.
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#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <riscv/allwinner/sunxi-d1s-t113.dtsi>
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#include <riscv/allwinner/sunxi-d1-t113.dtsi>
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/ {
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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clocks = <&ccu CLK_CPUX>;
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clock-names = "cpu";
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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clocks = <&ccu CLK_CPUX>;
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clock-names = "cpu";
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};
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};
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gic: interrupt-controller@1c81000 {
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compatible = "arm,gic-400";
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reg = <0x03021000 0x1000>,
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<0x03022000 0x2000>,
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<0x03024000 0x2000>,
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<0x03026000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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};
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