141 lines
4.2 KiB
YAML
141 lines
4.2 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/ti,tlv320adc3xxx.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments TLV320ADC3001/TLV320ADC3101 Stereo ADC
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maintainers:
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- Ricard Wanderlof <ricardw@axis.com>
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description: |
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Texas Instruments TLV320ADC3001 and TLV320ADC3101 Stereo ADC
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https://www.ti.com/product/TLV320ADC3001
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https://www.ti.com/product/TLV320ADC3101
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allOf:
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- $ref: dai-common.yaml#
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properties:
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compatible:
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enum:
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- ti,tlv320adc3001
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- ti,tlv320adc3101
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reg:
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maxItems: 1
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description: I2C address
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'#sound-dai-cells':
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const: 0
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'#gpio-cells':
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const: 2
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gpio-controller: true
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reset-gpios:
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maxItems: 1
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description: GPIO pin used for codec reset (RESET pin)
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clocks:
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maxItems: 1
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description: Master clock (MCLK)
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ti,dmdin-gpio1:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum:
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- 0 # ADC3XXX_GPIO_DISABLED - I/O buffers powered down and not used
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- 1 # ADC3XXX_GPIO_INPUT - Various non-GPIO input functions
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- 2 # ADC3XXX_GPIO_GPI - General purpose input
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- 3 # ADC3XXX_GPIO_GPO - General purpose output
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- 4 # ADC3XXX_GPIO_CLKOUT - Clock source set in CLKOUT_MUX reg
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- 5 # ADC3XXX_GPIO_INT1 - INT1 output
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- 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Codec interface secondary BCLK
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- 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK
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default: 0
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description: |
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Configuration for DMDIN/GPIO1 pin.
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When ADC3XXX_GPIO_GPO is configured, this causes corresponding the
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ALSA control "GPIOx Output" to appear, as a switch control.
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ti,dmclk-gpio2:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum:
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- 0 # ADC3XXX_GPIO_DISABLED - I/O buffers powered down and not used
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- 1 # ADC3XXX_GPIO_INPUT - Various non-GPIO input functions
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- 2 # ADC3XXX_GPIO_GPI - General purpose input
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- 3 # ADC3XXX_GPIO_GPO - General purpose output
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- 4 # ADC3XXX_GPIO_CLKOUT - Clock source set in CLKOUT_MUX reg
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- 5 # ADC3XXX_GPIO_INT1 - INT1 output
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- 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Codec interface secondary BCLK
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- 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK
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default: 0
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description: |
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Configuration for DMCLK/GPIO2 pin.
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When ADC3XXX_GPIO_GPO is configured, this causes corresponding the
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ALSA control "GPIOx Output" to appear, as a switch control.
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Note that there is currently no support for reading the GPIO pins as
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inputs.
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ti,micbias1-vg:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum:
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- 0 # ADC3XXX_MICBIAS_OFF - Mic bias is powered down
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- 1 # ADC3XXX_MICBIAS_2_0V - Mic bias is set to 2.0V
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- 2 # ADC3XXX_MICBIAS_2_5V - Mic bias is set to 2.5V
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- 3 # ADC3XXX_MICBIAS_AVDD - Mic bias is same as AVDD supply
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default: 0
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description: |
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Mic bias voltage output on MICBIAS1 pin
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ti,micbias2-vg:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum:
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- 0 # ADC3XXX_MICBIAS_OFF - Mic bias is powered down
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- 1 # ADC3XXX_MICBIAS_2_0V - Mic bias is set to 2.0V
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- 2 # ADC3XXX_MICBIAS_2_5V - Mic bias is set to 2.5V
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- 3 # ADC3XXX_MICBIAS_AVDD - Mic bias is same as AVDD supply
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default: 0
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description: |
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Mic bias voltage output on MICBIAS2 pin
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required:
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- compatible
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- reg
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/sound/tlv320adc3xxx.h>
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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tlv320adc3101: audio-codec@18 {
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compatible = "ti,tlv320adc3101";
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reg = <0x18>;
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reset-gpios = <&gpio_pc 3 GPIO_ACTIVE_LOW>;
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clocks = <&audio_mclk>;
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gpio-controller;
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#gpio-cells = <2>;
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ti,dmdin-gpio1 = <ADC3XXX_GPIO_GPO>;
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ti,micbias1-vg = <ADC3XXX_MICBIAS_AVDD>;
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};
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};
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audio_mclk: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24576000>;
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};
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...
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