113 lines
2.6 KiB
YAML
113 lines
2.6 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung SoC series UFS PHY
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maintainers:
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- Alim Akhtar <alim.akhtar@samsung.com>
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properties:
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"#phy-cells":
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const: 0
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compatible:
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enum:
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- samsung,exynos7-ufs-phy
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- samsung,exynosautov9-ufs-phy
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- tesla,fsd-ufs-phy
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reg:
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maxItems: 1
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reg-names:
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items:
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- const: phy-pma
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clocks:
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minItems: 1
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maxItems: 4
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clock-names:
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minItems: 1
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maxItems: 4
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samsung,pmu-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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items:
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minItems: 1
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items:
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- description: phandle for PMU system controller interface, used to
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control pmu registers bits for ufs m-phy
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- description: offset of the pmu control register
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description:
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It can be phandle/offset pair. The second cell which can represent an
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offset is optional.
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required:
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- "#phy-cells"
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- samsung,pmu-syscon
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7-ufs-phy
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then:
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properties:
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clocks:
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items:
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- description: PLL reference clock
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- description: symbol clock for input symbol (rx0-ch0 symbol clock)
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- description: symbol clock for input symbol (rx1-ch1 symbol clock)
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- description: symbol clock for output symbol (tx0 symbol clock)
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clock-names:
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items:
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- const: ref_clk
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- const: rx1_symbol_clk
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- const: rx0_symbol_clk
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- const: tx0_symbol_clk
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else:
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properties:
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clocks:
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items:
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- description: PLL reference clock
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clock-names:
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items:
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- const: ref_clk
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos7-clk.h>
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ufs_phy: ufs-phy@15571800 {
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compatible = "samsung,exynos7-ufs-phy";
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reg = <0x15571800 0x240>;
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reg-names = "phy-pma";
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samsung,pmu-syscon = <&pmu_system_controller>;
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#phy-cells = <0>;
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clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
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<&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
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<&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
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<&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
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clock-names = "ref_clk", "rx1_symbol_clk",
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"rx0_symbol_clk", "tx0_symbol_clk";
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};
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...
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