63 lines
1.6 KiB
YAML
63 lines
1.6 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on IPQ9574
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Anusha Rao <quic_anusha@quicinc.com>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on IPQ9574
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See also::
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include/dt-bindings/clock/qcom,ipq9574-gcc.h
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include/dt-bindings/reset/qcom,ipq9574-gcc.h
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properties:
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compatible:
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const: qcom,ipq9574-gcc
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: Bias PLL ubi clock source
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- description: PCIE30 PHY0 pipe clock source
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- description: PCIE30 PHY1 pipe clock source
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- description: PCIE30 PHY2 pipe clock source
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- description: PCIE30 PHY3 pipe clock source
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- description: USB3 PHY pipe clock source
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required:
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- compatible
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- clocks
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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clock-controller@1800000 {
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compatible = "qcom,ipq9574-gcc";
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reg = <0x01800000 0x80000>;
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clocks = <&xo_board_clk>,
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<&sleep_clk>,
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<&bias_pll_ubi_nc_clk>,
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<&pcie30_phy0_pipe_clk>,
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<&pcie30_phy1_pipe_clk>,
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<&pcie30_phy2_pipe_clk>,
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<&pcie30_phy3_pipe_clk>,
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<&usb3phy_0_cc_pipe_clk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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