110 lines
2.8 KiB
YAML
110 lines
2.8 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller on SM8150/SM8250/SM8350
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maintainers:
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- Jonathan Marek <jonathan@marek.ca>
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description: |
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Qualcomm display clock control module provides the clocks, resets and power
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domains on SM8150/SM8250/SM8350.
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See also::
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include/dt-bindings/clock/qcom,dispcc-sm8150.h
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include/dt-bindings/clock/qcom,dispcc-sm8250.h
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include/dt-bindings/clock/qcom,dispcc-sm8350.h
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properties:
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compatible:
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enum:
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- qcom,sc8180x-dispcc
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- qcom,sm8150-dispcc
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- qcom,sm8250-dispcc
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- qcom,sm8350-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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- description: Byte clock from DSI PHY1
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- description: Pixel clock from DSI PHY1
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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clock-names:
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items:
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- const: bi_tcxo
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi0_phy_pll_out_dsiclk
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- const: dsi1_phy_pll_out_byteclk
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- const: dsi1_phy_pll_out_dsiclk
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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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power-domains:
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description:
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A phandle and PM domain specifier for the MMCX power domain.
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maxItems: 1
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required-opps:
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description:
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A phandle to an OPP node describing required MMCX performance point.
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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clock-controller@af00000 {
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compatible = "qcom,sm8250-dispcc";
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reg = <0x0af00000 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>,
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<&dsi1_phy 0>,
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<&dsi1_phy 1>,
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<&dp_phy 0>,
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<&dp_phy 1>;
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clock-names = "bi_tcxo",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dsi1_phy_pll_out_byteclk",
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"dsi1_phy_pll_out_dsiclk",
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"dp_phy_pll_link_clk",
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"dp_phy_pll_vco_div_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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...
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