124 lines
3.4 KiB
YAML
124 lines
3.4 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ata/ahci-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Common Properties for Serial ATA AHCI controllers
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maintainers:
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- Hans de Goede <hdegoede@redhat.com>
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- Damien Le Moal <dlemoal@kernel.org>
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description:
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This document defines device tree properties for a common AHCI SATA
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controller implementation. It's hardware interface is supposed to
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conform to the technical standard defined by Intel (see Serial ATA
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Advanced Host Controller Interface specification for details). The
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document doesn't constitute a DT-node binding by itself but merely
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defines a set of common properties for the AHCI-compatible devices.
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select: false
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allOf:
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- $ref: sata-common.yaml#
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properties:
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reg:
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description:
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Generic AHCI registers space conforming to the Serial ATA AHCI
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specification.
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reg-names:
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description: CSR space IDs
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contains:
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const: ahci
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interrupts:
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description:
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Generic AHCI state change interrupt. Can be implemented either as a
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single line attached to the controller or as a set of the signals
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indicating the particular port events.
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minItems: 1
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maxItems: 32
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ahci-supply:
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description: Power regulator for AHCI controller
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target-supply:
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description: Power regulator for SATA target device
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phy-supply:
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description: Power regulator for SATA PHY
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phys:
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description: Reference to the SATA PHY node
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maxItems: 1
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phy-names:
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const: sata-phy
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hba-cap:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Bitfield of the HBA generic platform capabilities like Staggered
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Spin-up or Mechanical Presence Switch support. It can be used to
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appropriately initialize the HWinit fields of the HBA CAP register
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in case if the system firmware hasn't done it.
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ports-implemented:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Mask that indicates which ports the HBA supports. Useful if PI is not
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programmed by the BIOS, which is true for some embedded SoC's.
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patternProperties:
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"^sata-port@[0-9a-f]+$":
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$ref: '#/$defs/ahci-port'
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description:
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It is optionally possible to describe the ports as sub-nodes so
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to enable each port independently when dealing with multiple PHYs.
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required:
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- reg
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- interrupts
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additionalProperties: true
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$defs:
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ahci-port:
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$ref: /schemas/ata/sata-common.yaml#/$defs/sata-port
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properties:
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reg:
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description:
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AHCI SATA port identifier. By design AHCI controller can't have
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more than 32 ports due to the CAP.NP fields and PI register size
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constraints.
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minimum: 0
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maximum: 31
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phys:
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description: Individual AHCI SATA port PHY
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maxItems: 1
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phy-names:
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description: AHCI SATA port PHY ID
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const: sata-phy
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target-supply:
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description: Power regulator for SATA port target device
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hba-port-cap:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Bitfield of the HBA port-specific platform capabilities like Hot
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plugging, eSATA, FIS-based Switching, etc (see AHCI specification
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for details). It can be used to initialize the HWinit fields of
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the PxCMD register in case if the system firmware hasn't done it.
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required:
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- reg
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...
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