74 lines
1.8 KiB
C
74 lines
1.8 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2023 Intel Corporation. All rights reserved.
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*/
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#ifndef __SOUND_SOC_SOF_IPC4_TELEMETRY_H
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#define __SOUND_SOC_SOF_IPC4_TELEMETRY_H
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/* Target code */
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enum sof_ipc4_coredump_tgt_code {
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COREDUMP_TGT_UNKNOWN = 0,
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COREDUMP_TGT_X86,
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COREDUMP_TGT_X86_64,
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COREDUMP_TGT_ARM_CORTEX_M,
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COREDUMP_TGT_RISC_V,
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COREDUMP_TGT_XTENSA,
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};
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#define COREDUMP_ARCH_HDR_ID 'A'
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#define COREDUMP_HDR_ID0 'Z'
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#define COREDUMP_HDR_ID1 'E'
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#define XTENSA_BLOCK_HDR_VER 2
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#define XTENSA_CORE_DUMP_SEPARATOR 0x0DEC0DEB
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#define XTENSA_CORE_AR_REGS_COUNT 16
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#define XTENSA_SOC_INTEL_ADSP 3
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#define XTENSA_TOOL_CHAIN_ZEPHYR 1
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#define XTENSA_TOOL_CHAIN_XCC 2
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/* Coredump header */
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struct sof_ipc4_coredump_hdr {
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/* 'Z', 'E' as identifier of file */
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char id[2];
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/* Identify the version of the header */
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u16 hdr_version;
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/* Indicate which target (e.g. architecture or SoC) */
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u16 tgt_code;
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/* Size of uintptr_t in power of 2. (e.g. 5 for 32-bit, 6 for 64-bit) */
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u8 ptr_size_bits;
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u8 flag;
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/* Reason for the fatal error */
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u32 reason;
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} __packed;
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/* Architecture-specific block header */
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struct sof_ipc4_coredump_arch_hdr {
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/* COREDUMP_ARCH_HDR_ID to indicate this is a architecture-specific block */
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char id;
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/* Identify the version of this block */
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u16 hdr_version;
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/* Number of bytes following the header */
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u16 num_bytes;
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} __packed;
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struct sof_ipc4_telemetry_slot_data {
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u32 separator;
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struct sof_ipc4_coredump_hdr hdr;
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struct sof_ipc4_coredump_arch_hdr arch_hdr;
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u32 arch_data[];
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} __packed;
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void sof_ipc4_create_exception_debugfs_node(struct snd_sof_dev *sdev);
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#endif
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