413 lines
12 KiB
C
413 lines
12 KiB
C
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2023 Advanced Micro Devices, Inc.
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//
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// Authors: Syed Saba Kareem <Syed.SabaKareem@amd.com>
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//
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/*
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* Common file to be used by amd platforms
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*/
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#include "amd.h"
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#include <linux/pci.h>
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#include <linux/export.h>
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#define ACP_RENOIR_PDM_ADDR 0x02
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#define ACP_REMBRANDT_PDM_ADDR 0x03
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#define ACP63_PDM_ADDR 0x02
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#define ACP70_PDM_ADDR 0x02
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void acp_enable_interrupts(struct acp_dev_data *adata)
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{
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struct acp_resource *rsrc = adata->rsrc;
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u32 ext_intr_ctrl;
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writel(0x01, ACP_EXTERNAL_INTR_ENB(adata));
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ext_intr_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, rsrc->irqp_used));
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ext_intr_ctrl |= ACP_ERROR_MASK;
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writel(ext_intr_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, rsrc->irqp_used));
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}
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EXPORT_SYMBOL_NS_GPL(acp_enable_interrupts, SND_SOC_ACP_COMMON);
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void acp_disable_interrupts(struct acp_dev_data *adata)
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{
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struct acp_resource *rsrc = adata->rsrc;
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writel(ACP_EXT_INTR_STAT_CLEAR_MASK, ACP_EXTERNAL_INTR_STAT(adata, rsrc->irqp_used));
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writel(0x00, ACP_EXTERNAL_INTR_ENB(adata));
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}
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EXPORT_SYMBOL_NS_GPL(acp_disable_interrupts, SND_SOC_ACP_COMMON);
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static void set_acp_pdm_ring_buffer(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct acp_stream *stream = runtime->private_data;
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struct device *dev = dai->component->dev;
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struct acp_dev_data *adata = dev_get_drvdata(dev);
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u32 physical_addr, pdm_size, period_bytes;
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period_bytes = frames_to_bytes(runtime, runtime->period_size);
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pdm_size = frames_to_bytes(runtime, runtime->buffer_size);
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physical_addr = stream->reg_offset + MEM_WINDOW_START;
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/* Init ACP PDM Ring buffer */
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writel(physical_addr, adata->acp_base + ACP_WOV_RX_RINGBUFADDR);
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writel(pdm_size, adata->acp_base + ACP_WOV_RX_RINGBUFSIZE);
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writel(period_bytes, adata->acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
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writel(0x01, adata->acp_base + ACPAXI2AXI_ATU_CTRL);
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}
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static void set_acp_pdm_clk(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct device *dev = dai->component->dev;
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struct acp_dev_data *adata = dev_get_drvdata(dev);
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unsigned int pdm_ctrl;
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/* Enable default ACP PDM clk */
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writel(PDM_CLK_FREQ_MASK, adata->acp_base + ACP_WOV_CLK_CTRL);
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pdm_ctrl = readl(adata->acp_base + ACP_WOV_MISC_CTRL);
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pdm_ctrl |= PDM_MISC_CTRL_MASK;
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writel(pdm_ctrl, adata->acp_base + ACP_WOV_MISC_CTRL);
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set_acp_pdm_ring_buffer(substream, dai);
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}
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void restore_acp_pdm_params(struct snd_pcm_substream *substream,
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struct acp_dev_data *adata)
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{
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struct snd_soc_dai *dai;
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struct snd_soc_pcm_runtime *soc_runtime;
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u32 ext_int_ctrl;
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soc_runtime = snd_soc_substream_to_rtd(substream);
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dai = snd_soc_rtd_to_cpu(soc_runtime, 0);
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/* Programming channel mask and sampling rate */
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writel(adata->ch_mask, adata->acp_base + ACP_WOV_PDM_NO_OF_CHANNELS);
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writel(PDM_DEC_64, adata->acp_base + ACP_WOV_PDM_DECIMATION_FACTOR);
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/* Enabling ACP Pdm interuppts */
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ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, 0));
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ext_int_ctrl |= PDM_DMA_INTR_MASK;
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writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, 0));
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set_acp_pdm_clk(substream, dai);
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}
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EXPORT_SYMBOL_NS_GPL(restore_acp_pdm_params, SND_SOC_ACP_COMMON);
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static int set_acp_i2s_dma_fifo(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct device *dev = dai->component->dev;
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struct acp_dev_data *adata = dev_get_drvdata(dev);
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struct acp_resource *rsrc = adata->rsrc;
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struct acp_stream *stream = substream->runtime->private_data;
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u32 reg_dma_size, reg_fifo_size, reg_fifo_addr;
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u32 phy_addr, acp_fifo_addr, ext_int_ctrl;
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unsigned int dir = substream->stream;
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switch (dai->driver->id) {
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case I2S_SP_INSTANCE:
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if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
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reg_dma_size = ACP_I2S_TX_DMA_SIZE;
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acp_fifo_addr = rsrc->sram_pte_offset +
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SP_PB_FIFO_ADDR_OFFSET;
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reg_fifo_addr = ACP_I2S_TX_FIFOADDR;
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reg_fifo_size = ACP_I2S_TX_FIFOSIZE;
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phy_addr = I2S_SP_TX_MEM_WINDOW_START + stream->reg_offset;
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writel(phy_addr, adata->acp_base + ACP_I2S_TX_RINGBUFADDR);
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} else {
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reg_dma_size = ACP_I2S_RX_DMA_SIZE;
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acp_fifo_addr = rsrc->sram_pte_offset +
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SP_CAPT_FIFO_ADDR_OFFSET;
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reg_fifo_addr = ACP_I2S_RX_FIFOADDR;
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reg_fifo_size = ACP_I2S_RX_FIFOSIZE;
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phy_addr = I2S_SP_RX_MEM_WINDOW_START + stream->reg_offset;
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writel(phy_addr, adata->acp_base + ACP_I2S_RX_RINGBUFADDR);
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}
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break;
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case I2S_BT_INSTANCE:
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if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
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reg_dma_size = ACP_BT_TX_DMA_SIZE;
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acp_fifo_addr = rsrc->sram_pte_offset +
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BT_PB_FIFO_ADDR_OFFSET;
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reg_fifo_addr = ACP_BT_TX_FIFOADDR;
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reg_fifo_size = ACP_BT_TX_FIFOSIZE;
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phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
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writel(phy_addr, adata->acp_base + ACP_BT_TX_RINGBUFADDR);
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} else {
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reg_dma_size = ACP_BT_RX_DMA_SIZE;
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acp_fifo_addr = rsrc->sram_pte_offset +
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BT_CAPT_FIFO_ADDR_OFFSET;
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reg_fifo_addr = ACP_BT_RX_FIFOADDR;
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reg_fifo_size = ACP_BT_RX_FIFOSIZE;
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phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
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writel(phy_addr, adata->acp_base + ACP_BT_RX_RINGBUFADDR);
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}
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break;
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case I2S_HS_INSTANCE:
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if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
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reg_dma_size = ACP_HS_TX_DMA_SIZE;
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acp_fifo_addr = rsrc->sram_pte_offset +
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HS_PB_FIFO_ADDR_OFFSET;
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reg_fifo_addr = ACP_HS_TX_FIFOADDR;
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reg_fifo_size = ACP_HS_TX_FIFOSIZE;
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phy_addr = I2S_HS_TX_MEM_WINDOW_START + stream->reg_offset;
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writel(phy_addr, adata->acp_base + ACP_HS_TX_RINGBUFADDR);
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} else {
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reg_dma_size = ACP_HS_RX_DMA_SIZE;
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acp_fifo_addr = rsrc->sram_pte_offset +
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HS_CAPT_FIFO_ADDR_OFFSET;
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reg_fifo_addr = ACP_HS_RX_FIFOADDR;
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reg_fifo_size = ACP_HS_RX_FIFOSIZE;
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phy_addr = I2S_HS_RX_MEM_WINDOW_START + stream->reg_offset;
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writel(phy_addr, adata->acp_base + ACP_HS_RX_RINGBUFADDR);
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}
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break;
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default:
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dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
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return -EINVAL;
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}
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writel(DMA_SIZE, adata->acp_base + reg_dma_size);
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writel(acp_fifo_addr, adata->acp_base + reg_fifo_addr);
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writel(FIFO_SIZE, adata->acp_base + reg_fifo_size);
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ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, rsrc->irqp_used));
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ext_int_ctrl |= BIT(I2S_RX_THRESHOLD(rsrc->offset)) |
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BIT(BT_RX_THRESHOLD(rsrc->offset)) |
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BIT(I2S_TX_THRESHOLD(rsrc->offset)) |
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BIT(BT_TX_THRESHOLD(rsrc->offset)) |
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BIT(HS_RX_THRESHOLD(rsrc->offset)) |
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BIT(HS_TX_THRESHOLD(rsrc->offset));
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writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, rsrc->irqp_used));
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return 0;
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}
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int restore_acp_i2s_params(struct snd_pcm_substream *substream,
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struct acp_dev_data *adata,
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struct acp_stream *stream)
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{
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struct snd_soc_dai *dai;
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struct snd_soc_pcm_runtime *soc_runtime;
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u32 tdm_fmt, reg_val, fmt_reg, val;
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soc_runtime = snd_soc_substream_to_rtd(substream);
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dai = snd_soc_rtd_to_cpu(soc_runtime, 0);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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tdm_fmt = adata->tdm_tx_fmt[stream->dai_id - 1];
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switch (stream->dai_id) {
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case I2S_BT_INSTANCE:
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reg_val = ACP_BTTDM_ITER;
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fmt_reg = ACP_BTTDM_TXFRMT;
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break;
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case I2S_SP_INSTANCE:
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reg_val = ACP_I2STDM_ITER;
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fmt_reg = ACP_I2STDM_TXFRMT;
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break;
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case I2S_HS_INSTANCE:
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reg_val = ACP_HSTDM_ITER;
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fmt_reg = ACP_HSTDM_TXFRMT;
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break;
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default:
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pr_err("Invalid dai id %x\n", stream->dai_id);
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return -EINVAL;
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}
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val = adata->xfer_tx_resolution[stream->dai_id - 1] << 3;
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} else {
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tdm_fmt = adata->tdm_rx_fmt[stream->dai_id - 1];
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switch (stream->dai_id) {
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case I2S_BT_INSTANCE:
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reg_val = ACP_BTTDM_IRER;
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fmt_reg = ACP_BTTDM_RXFRMT;
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break;
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case I2S_SP_INSTANCE:
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reg_val = ACP_I2STDM_IRER;
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fmt_reg = ACP_I2STDM_RXFRMT;
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break;
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case I2S_HS_INSTANCE:
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reg_val = ACP_HSTDM_IRER;
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fmt_reg = ACP_HSTDM_RXFRMT;
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break;
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default:
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pr_err("Invalid dai id %x\n", stream->dai_id);
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return -EINVAL;
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}
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val = adata->xfer_rx_resolution[stream->dai_id - 1] << 3;
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}
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writel(val, adata->acp_base + reg_val);
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if (adata->tdm_mode == TDM_ENABLE) {
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writel(tdm_fmt, adata->acp_base + fmt_reg);
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val = readl(adata->acp_base + reg_val);
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writel(val | 0x2, adata->acp_base + reg_val);
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}
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return set_acp_i2s_dma_fifo(substream, dai);
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}
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EXPORT_SYMBOL_NS_GPL(restore_acp_i2s_params, SND_SOC_ACP_COMMON);
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static int acp_power_on(struct acp_chip_info *chip)
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{
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u32 val, acp_pgfsm_stat_reg, acp_pgfsm_ctrl_reg;
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void __iomem *base;
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base = chip->base;
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switch (chip->acp_rev) {
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case ACP3X_DEV:
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acp_pgfsm_stat_reg = ACP_PGFSM_STATUS;
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acp_pgfsm_ctrl_reg = ACP_PGFSM_CONTROL;
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break;
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case ACP6X_DEV:
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acp_pgfsm_stat_reg = ACP6X_PGFSM_STATUS;
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acp_pgfsm_ctrl_reg = ACP6X_PGFSM_CONTROL;
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break;
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case ACP63_DEV:
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acp_pgfsm_stat_reg = ACP63_PGFSM_STATUS;
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acp_pgfsm_ctrl_reg = ACP63_PGFSM_CONTROL;
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break;
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case ACP70_DEV:
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acp_pgfsm_stat_reg = ACP70_PGFSM_STATUS;
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acp_pgfsm_ctrl_reg = ACP70_PGFSM_CONTROL;
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break;
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default:
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return -EINVAL;
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}
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val = readl(base + acp_pgfsm_stat_reg);
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if (val == ACP_POWERED_ON)
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return 0;
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if ((val & ACP_PGFSM_STATUS_MASK) != ACP_POWER_ON_IN_PROGRESS)
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writel(ACP_PGFSM_CNTL_POWER_ON_MASK, base + acp_pgfsm_ctrl_reg);
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return readl_poll_timeout(base + acp_pgfsm_stat_reg, val,
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!val, DELAY_US, ACP_TIMEOUT);
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}
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static int acp_reset(void __iomem *base)
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{
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u32 val;
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int ret;
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writel(1, base + ACP_SOFT_RESET);
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ret = readl_poll_timeout(base + ACP_SOFT_RESET, val, val & ACP_SOFT_RST_DONE_MASK,
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DELAY_US, ACP_TIMEOUT);
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if (ret)
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return ret;
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writel(0, base + ACP_SOFT_RESET);
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return readl_poll_timeout(base + ACP_SOFT_RESET, val, !val, DELAY_US, ACP_TIMEOUT);
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}
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int acp_init(struct acp_chip_info *chip)
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{
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int ret;
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/* power on */
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ret = acp_power_on(chip);
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if (ret) {
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pr_err("ACP power on failed\n");
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|
|
return ret;
|
||
|
|
}
|
||
|
|
writel(0x01, chip->base + ACP_CONTROL);
|
||
|
|
|
||
|
|
/* Reset */
|
||
|
|
ret = acp_reset(chip->base);
|
||
|
|
if (ret) {
|
||
|
|
pr_err("ACP reset failed\n");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_NS_GPL(acp_init, SND_SOC_ACP_COMMON);
|
||
|
|
|
||
|
|
int acp_deinit(struct acp_chip_info *chip)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
/* Reset */
|
||
|
|
ret = acp_reset(chip->base);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
if (chip->acp_rev != ACP70_DEV)
|
||
|
|
writel(0, chip->base + ACP_CONTROL);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_NS_GPL(acp_deinit, SND_SOC_ACP_COMMON);
|
||
|
|
|
||
|
|
int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data)
|
||
|
|
{
|
||
|
|
pci_write_config_dword(dev, 0x60, smn_addr);
|
||
|
|
pci_write_config_dword(dev, 0x64, data);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_NS_GPL(smn_write, SND_SOC_ACP_COMMON);
|
||
|
|
|
||
|
|
int smn_read(struct pci_dev *dev, u32 smn_addr)
|
||
|
|
{
|
||
|
|
u32 data;
|
||
|
|
|
||
|
|
pci_write_config_dword(dev, 0x60, smn_addr);
|
||
|
|
pci_read_config_dword(dev, 0x64, &data);
|
||
|
|
return data;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_NS_GPL(smn_read, SND_SOC_ACP_COMMON);
|
||
|
|
|
||
|
|
int check_acp_pdm(struct pci_dev *pci, struct acp_chip_info *chip)
|
||
|
|
{
|
||
|
|
struct acpi_device *pdm_dev;
|
||
|
|
const union acpi_object *obj;
|
||
|
|
u32 pdm_addr, val;
|
||
|
|
|
||
|
|
val = readl(chip->base + ACP_PIN_CONFIG);
|
||
|
|
switch (val) {
|
||
|
|
case ACP_CONFIG_4:
|
||
|
|
case ACP_CONFIG_5:
|
||
|
|
case ACP_CONFIG_6:
|
||
|
|
case ACP_CONFIG_7:
|
||
|
|
case ACP_CONFIG_8:
|
||
|
|
case ACP_CONFIG_10:
|
||
|
|
case ACP_CONFIG_11:
|
||
|
|
case ACP_CONFIG_12:
|
||
|
|
case ACP_CONFIG_13:
|
||
|
|
case ACP_CONFIG_14:
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
switch (chip->acp_rev) {
|
||
|
|
case ACP3X_DEV:
|
||
|
|
pdm_addr = ACP_RENOIR_PDM_ADDR;
|
||
|
|
break;
|
||
|
|
case ACP6X_DEV:
|
||
|
|
pdm_addr = ACP_REMBRANDT_PDM_ADDR;
|
||
|
|
break;
|
||
|
|
case ACP63_DEV:
|
||
|
|
pdm_addr = ACP63_PDM_ADDR;
|
||
|
|
break;
|
||
|
|
case ACP70_DEV:
|
||
|
|
pdm_addr = ACP70_PDM_ADDR;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
pdm_dev = acpi_find_child_device(ACPI_COMPANION(&pci->dev), pdm_addr, 0);
|
||
|
|
if (pdm_dev) {
|
||
|
|
if (!acpi_dev_get_property(pdm_dev, "acp-audio-device-type",
|
||
|
|
ACPI_TYPE_INTEGER, &obj) &&
|
||
|
|
obj->integer.value == pdm_addr)
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_NS_GPL(check_acp_pdm, SND_SOC_ACP_COMMON);
|
||
|
|
|
||
|
|
MODULE_LICENSE("Dual BSD/GPL");
|