292 lines
7.5 KiB
C
292 lines
7.5 KiB
C
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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/*
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* Wave5 series multi-standard codec IP - platform driver
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*
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* Copyright (C) 2021-2023 CHIPS&MEDIA INC
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/firmware.h>
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#include <linux/interrupt.h>
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#include "wave5-vpu.h"
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#include "wave5-regdefine.h"
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#include "wave5-vpuconfig.h"
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#include "wave5.h"
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#define VPU_PLATFORM_DEVICE_NAME "vdec"
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#define VPU_CLK_NAME "vcodec"
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#define WAVE5_IS_ENC BIT(0)
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#define WAVE5_IS_DEC BIT(1)
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struct wave5_match_data {
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int flags;
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const char *fw_name;
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};
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int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout)
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{
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int ret;
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ret = wait_for_completion_timeout(&inst->irq_done,
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msecs_to_jiffies(timeout));
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if (!ret)
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return -ETIMEDOUT;
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reinit_completion(&inst->irq_done);
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return 0;
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}
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static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id)
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{
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u32 seq_done;
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u32 cmd_done;
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u32 irq_reason;
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struct vpu_instance *inst;
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struct vpu_device *dev = dev_id;
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if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS)) {
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irq_reason = wave5_vdi_read_register(dev, W5_VPU_VINT_REASON);
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wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_reason);
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wave5_vdi_write_register(dev, W5_VPU_VINT_CLEAR, 0x1);
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list_for_each_entry(inst, &dev->instances, list) {
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seq_done = wave5_vdi_read_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO);
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cmd_done = wave5_vdi_read_register(dev, W5_RET_QUEUE_CMD_DONE_INST);
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if (irq_reason & BIT(INT_WAVE5_INIT_SEQ) ||
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irq_reason & BIT(INT_WAVE5_ENC_SET_PARAM)) {
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if (seq_done & BIT(inst->id)) {
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seq_done &= ~BIT(inst->id);
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wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO,
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seq_done);
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complete(&inst->irq_done);
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}
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}
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if (irq_reason & BIT(INT_WAVE5_DEC_PIC) ||
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irq_reason & BIT(INT_WAVE5_ENC_PIC)) {
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if (cmd_done & BIT(inst->id)) {
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cmd_done &= ~BIT(inst->id);
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wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST,
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cmd_done);
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inst->ops->finish_process(inst);
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}
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}
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wave5_vpu_clear_interrupt(inst, irq_reason);
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}
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}
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return IRQ_HANDLED;
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}
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static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name,
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u32 *revision)
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{
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const struct firmware *fw;
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int ret;
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unsigned int product_id;
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ret = request_firmware(&fw, fw_name, dev);
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if (ret) {
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dev_err(dev, "request_firmware, fail: %d\n", ret);
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return ret;
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}
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ret = wave5_vpu_init_with_bitcode(dev, (u8 *)fw->data, fw->size);
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if (ret) {
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dev_err(dev, "vpu_init_with_bitcode, fail: %d\n", ret);
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release_firmware(fw);
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return ret;
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}
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release_firmware(fw);
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ret = wave5_vpu_get_version_info(dev, revision, &product_id);
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if (ret) {
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dev_err(dev, "vpu_get_version_info fail: %d\n", ret);
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return ret;
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}
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dev_dbg(dev, "%s: enum product_id: %08x, fw revision: %u\n",
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__func__, product_id, *revision);
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return 0;
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}
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static int wave5_vpu_probe(struct platform_device *pdev)
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{
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int ret;
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struct vpu_device *dev;
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const struct wave5_match_data *match_data;
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u32 fw_revision;
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match_data = device_get_match_data(&pdev->dev);
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if (!match_data) {
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dev_err(&pdev->dev, "missing device match data\n");
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return -EINVAL;
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}
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/* physical addresses limited to 32 bits */
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ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
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if (ret) {
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dev_err(&pdev->dev, "Failed to set DMA mask: %d\n", ret);
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return ret;
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}
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dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
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if (!dev)
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return -ENOMEM;
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dev->vdb_register = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(dev->vdb_register))
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return PTR_ERR(dev->vdb_register);
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ida_init(&dev->inst_ida);
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mutex_init(&dev->dev_lock);
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mutex_init(&dev->hw_lock);
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dev_set_drvdata(&pdev->dev, dev);
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dev->dev = &pdev->dev;
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ret = devm_clk_bulk_get_all(&pdev->dev, &dev->clks);
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/* continue without clock, assume externally managed */
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if (ret < 0) {
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dev_warn(&pdev->dev, "Getting clocks, fail: %d\n", ret);
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ret = 0;
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}
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dev->num_clks = ret;
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ret = clk_bulk_prepare_enable(dev->num_clks, dev->clks);
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if (ret) {
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dev_err(&pdev->dev, "Enabling clocks, fail: %d\n", ret);
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return ret;
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}
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ret = of_property_read_u32(pdev->dev.of_node, "sram-size",
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&dev->sram_size);
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if (ret) {
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dev_warn(&pdev->dev, "sram-size not found\n");
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dev->sram_size = 0;
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}
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dev->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0);
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if (!dev->sram_pool)
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dev_warn(&pdev->dev, "sram node not found\n");
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dev->product_code = wave5_vdi_read_register(dev, VPU_PRODUCT_CODE_REGISTER);
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ret = wave5_vdi_init(&pdev->dev);
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if (ret < 0) {
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dev_err(&pdev->dev, "wave5_vdi_init, fail: %d\n", ret);
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goto err_clk_dis;
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}
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dev->product = wave5_vpu_get_product_id(dev);
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INIT_LIST_HEAD(&dev->instances);
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ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
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if (ret) {
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dev_err(&pdev->dev, "v4l2_device_register, fail: %d\n", ret);
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goto err_vdi_release;
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}
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if (match_data->flags & WAVE5_IS_DEC) {
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ret = wave5_vpu_dec_register_device(dev);
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if (ret) {
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dev_err(&pdev->dev, "wave5_vpu_dec_register_device, fail: %d\n", ret);
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goto err_v4l2_unregister;
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}
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}
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if (match_data->flags & WAVE5_IS_ENC) {
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ret = wave5_vpu_enc_register_device(dev);
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if (ret) {
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dev_err(&pdev->dev, "wave5_vpu_enc_register_device, fail: %d\n", ret);
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goto err_dec_unreg;
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}
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}
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dev->irq = platform_get_irq(pdev, 0);
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if (dev->irq < 0) {
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dev_err(&pdev->dev, "failed to get irq resource\n");
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ret = -ENXIO;
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goto err_enc_unreg;
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}
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ret = devm_request_threaded_irq(&pdev->dev, dev->irq, NULL,
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wave5_vpu_irq_thread, IRQF_ONESHOT, "vpu_irq", dev);
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if (ret) {
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dev_err(&pdev->dev, "Register interrupt handler, fail: %d\n", ret);
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goto err_enc_unreg;
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}
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ret = wave5_vpu_load_firmware(&pdev->dev, match_data->fw_name, &fw_revision);
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if (ret) {
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dev_err(&pdev->dev, "wave5_vpu_load_firmware, fail: %d\n", ret);
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goto err_enc_unreg;
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}
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dev_info(&pdev->dev, "Added wave5 driver with caps: %s %s\n",
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(match_data->flags & WAVE5_IS_ENC) ? "'ENCODE'" : "",
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(match_data->flags & WAVE5_IS_DEC) ? "'DECODE'" : "");
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dev_info(&pdev->dev, "Product Code: 0x%x\n", dev->product_code);
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dev_info(&pdev->dev, "Firmware Revision: %u\n", fw_revision);
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return 0;
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err_enc_unreg:
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if (match_data->flags & WAVE5_IS_ENC)
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wave5_vpu_enc_unregister_device(dev);
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err_dec_unreg:
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if (match_data->flags & WAVE5_IS_DEC)
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wave5_vpu_dec_unregister_device(dev);
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err_v4l2_unregister:
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v4l2_device_unregister(&dev->v4l2_dev);
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err_vdi_release:
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wave5_vdi_release(&pdev->dev);
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err_clk_dis:
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clk_bulk_disable_unprepare(dev->num_clks, dev->clks);
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return ret;
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}
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static int wave5_vpu_remove(struct platform_device *pdev)
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{
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struct vpu_device *dev = dev_get_drvdata(&pdev->dev);
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mutex_destroy(&dev->dev_lock);
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mutex_destroy(&dev->hw_lock);
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clk_bulk_disable_unprepare(dev->num_clks, dev->clks);
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wave5_vpu_enc_unregister_device(dev);
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wave5_vpu_dec_unregister_device(dev);
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v4l2_device_unregister(&dev->v4l2_dev);
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wave5_vdi_release(&pdev->dev);
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ida_destroy(&dev->inst_ida);
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return 0;
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}
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static const struct wave5_match_data ti_wave521c_data = {
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.flags = WAVE5_IS_ENC | WAVE5_IS_DEC,
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.fw_name = "cnm/wave521c_k3_codec_fw.bin",
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};
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static const struct of_device_id wave5_dt_ids[] = {
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{ .compatible = "ti,j721s2-wave521c", .data = &ti_wave521c_data },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, wave5_dt_ids);
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static struct platform_driver wave5_vpu_driver = {
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.driver = {
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.name = VPU_PLATFORM_DEVICE_NAME,
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.of_match_table = of_match_ptr(wave5_dt_ids),
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},
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.probe = wave5_vpu_probe,
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.remove = wave5_vpu_remove,
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};
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module_platform_driver(wave5_vpu_driver);
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MODULE_DESCRIPTION("chips&media VPU V4L2 driver");
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MODULE_LICENSE("Dual BSD/GPL");
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