468 lines
12 KiB
C
468 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Axis Communications AB
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*
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* Datasheet: https://www.ti.com/lit/gpn/opt4001
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*
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* Device driver for the Texas Instruments OPT4001.
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*/
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#include <linux/bitfield.h>
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#include <linux/i2c.h>
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#include <linux/iio/iio.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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/* OPT4001 register set */
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#define OPT4001_LIGHT1_MSB 0x00
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#define OPT4001_LIGHT1_LSB 0x01
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#define OPT4001_CTRL 0x0A
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#define OPT4001_DEVICE_ID 0x11
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/* OPT4001 register mask */
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#define OPT4001_EXPONENT_MASK GENMASK(15, 12)
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#define OPT4001_MSB_MASK GENMASK(11, 0)
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#define OPT4001_LSB_MASK GENMASK(15, 8)
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#define OPT4001_COUNTER_MASK GENMASK(7, 4)
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#define OPT4001_CRC_MASK GENMASK(3, 0)
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/* OPT4001 device id mask */
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#define OPT4001_DEVICE_ID_MASK GENMASK(11, 0)
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/* OPT4001 control registers mask */
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#define OPT4001_CTRL_QWAKE_MASK GENMASK(15, 15)
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#define OPT4001_CTRL_RANGE_MASK GENMASK(13, 10)
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#define OPT4001_CTRL_CONV_TIME_MASK GENMASK(9, 6)
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#define OPT4001_CTRL_OPER_MODE_MASK GENMASK(5, 4)
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#define OPT4001_CTRL_LATCH_MASK GENMASK(3, 3)
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#define OPT4001_CTRL_INT_POL_MASK GENMASK(2, 2)
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#define OPT4001_CTRL_FAULT_COUNT GENMASK(0, 1)
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/* OPT4001 constants */
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#define OPT4001_DEVICE_ID_VAL 0x121
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/* OPT4001 operating modes */
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#define OPT4001_CTRL_OPER_MODE_OFF 0x0
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#define OPT4001_CTRL_OPER_MODE_FORCED 0x1
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#define OPT4001_CTRL_OPER_MODE_ONE_SHOT 0x2
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#define OPT4001_CTRL_OPER_MODE_CONTINUOUS 0x3
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/* OPT4001 conversion control register definitions */
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#define OPT4001_CTRL_CONVERSION_0_6MS 0x0
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#define OPT4001_CTRL_CONVERSION_1MS 0x1
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#define OPT4001_CTRL_CONVERSION_1_8MS 0x2
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#define OPT4001_CTRL_CONVERSION_3_4MS 0x3
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#define OPT4001_CTRL_CONVERSION_6_5MS 0x4
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#define OPT4001_CTRL_CONVERSION_12_7MS 0x5
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#define OPT4001_CTRL_CONVERSION_25MS 0x6
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#define OPT4001_CTRL_CONVERSION_50MS 0x7
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#define OPT4001_CTRL_CONVERSION_100MS 0x8
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#define OPT4001_CTRL_CONVERSION_200MS 0x9
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#define OPT4001_CTRL_CONVERSION_400MS 0xa
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#define OPT4001_CTRL_CONVERSION_800MS 0xb
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/* OPT4001 scale light level range definitions */
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#define OPT4001_CTRL_LIGHT_SCALE_AUTO 12
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/* OPT4001 default values */
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#define OPT4001_DEFAULT_CONVERSION_TIME OPT4001_CTRL_CONVERSION_800MS
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/*
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* The different packaging of OPT4001 has different constants used when calculating
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* lux values.
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*/
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struct opt4001_chip_info {
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int mul;
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int div;
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const char *name;
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};
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struct opt4001_chip {
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struct regmap *regmap;
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struct i2c_client *client;
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u8 int_time;
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const struct opt4001_chip_info *chip_info;
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};
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static const struct opt4001_chip_info opt4001_sot_5x3_info = {
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.mul = 4375,
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.div = 10000000,
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.name = "opt4001-sot-5x3"
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};
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static const struct opt4001_chip_info opt4001_picostar_info = {
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.mul = 3125,
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.div = 10000000,
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.name = "opt4001-picostar"
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};
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static const int opt4001_int_time_available[][2] = {
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{ 0, 600 },
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{ 0, 1000 },
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{ 0, 1800 },
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{ 0, 3400 },
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{ 0, 6500 },
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{ 0, 12700 },
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{ 0, 25000 },
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{ 0, 50000 },
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{ 0, 100000 },
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{ 0, 200000 },
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{ 0, 400000 },
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{ 0, 800000 },
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};
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/*
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* Conversion time is integration time + time to set register
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* this is used as integration time.
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*/
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static const int opt4001_int_time_reg[][2] = {
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{ 600, OPT4001_CTRL_CONVERSION_0_6MS },
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{ 1000, OPT4001_CTRL_CONVERSION_1MS },
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{ 1800, OPT4001_CTRL_CONVERSION_1_8MS },
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{ 3400, OPT4001_CTRL_CONVERSION_3_4MS },
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{ 6500, OPT4001_CTRL_CONVERSION_6_5MS },
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{ 12700, OPT4001_CTRL_CONVERSION_12_7MS },
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{ 25000, OPT4001_CTRL_CONVERSION_25MS },
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{ 50000, OPT4001_CTRL_CONVERSION_50MS },
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{ 100000, OPT4001_CTRL_CONVERSION_100MS },
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{ 200000, OPT4001_CTRL_CONVERSION_200MS },
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{ 400000, OPT4001_CTRL_CONVERSION_400MS },
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{ 800000, OPT4001_CTRL_CONVERSION_800MS },
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};
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static int opt4001_als_time_to_index(const u32 als_integration_time)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(opt4001_int_time_available); i++) {
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if (als_integration_time == opt4001_int_time_available[i][1])
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return i;
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}
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return -EINVAL;
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}
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static u8 opt4001_calculate_crc(u8 exp, u32 mantissa, u8 count)
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{
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u8 crc;
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crc = (hweight32(mantissa) + hweight32(exp) + hweight32(count)) % 2;
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crc |= ((hweight32(mantissa & 0xAAAAA) + hweight32(exp & 0xA)
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+ hweight32(count & 0xA)) % 2) << 1;
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crc |= ((hweight32(mantissa & 0x88888) + hweight32(exp & 0x8)
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+ hweight32(count & 0x8)) % 2) << 2;
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crc |= (hweight32(mantissa & 0x80808) % 2) << 3;
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return crc;
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}
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static int opt4001_read_lux_value(struct iio_dev *indio_dev,
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int *val, int *val2)
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{
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struct opt4001_chip *chip = iio_priv(indio_dev);
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struct device *dev = &chip->client->dev;
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unsigned int light1;
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unsigned int light2;
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u16 msb;
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u16 lsb;
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u8 exp;
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u8 count;
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u8 crc;
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u8 calc_crc;
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u64 lux_raw;
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int ret;
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ret = regmap_read(chip->regmap, OPT4001_LIGHT1_MSB, &light1);
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if (ret < 0) {
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dev_err(dev, "Failed to read data bytes");
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return ret;
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}
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ret = regmap_read(chip->regmap, OPT4001_LIGHT1_LSB, &light2);
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if (ret < 0) {
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dev_err(dev, "Failed to read data bytes");
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return ret;
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}
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count = FIELD_GET(OPT4001_COUNTER_MASK, light2);
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exp = FIELD_GET(OPT4001_EXPONENT_MASK, light1);
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crc = FIELD_GET(OPT4001_CRC_MASK, light2);
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msb = FIELD_GET(OPT4001_MSB_MASK, light1);
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lsb = FIELD_GET(OPT4001_LSB_MASK, light2);
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lux_raw = (msb << 8) + lsb;
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calc_crc = opt4001_calculate_crc(exp, lux_raw, count);
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if (calc_crc != crc)
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return -EIO;
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lux_raw = lux_raw << exp;
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lux_raw = lux_raw * chip->chip_info->mul;
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*val = div_u64_rem(lux_raw, chip->chip_info->div, val2);
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*val2 = *val2 * 100;
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return IIO_VAL_INT_PLUS_NANO;
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}
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static int opt4001_set_conf(struct opt4001_chip *chip)
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{
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struct device *dev = &chip->client->dev;
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u16 reg;
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int ret;
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reg = FIELD_PREP(OPT4001_CTRL_RANGE_MASK, OPT4001_CTRL_LIGHT_SCALE_AUTO);
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reg |= FIELD_PREP(OPT4001_CTRL_CONV_TIME_MASK, chip->int_time);
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reg |= FIELD_PREP(OPT4001_CTRL_OPER_MODE_MASK, OPT4001_CTRL_OPER_MODE_CONTINUOUS);
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ret = regmap_write(chip->regmap, OPT4001_CTRL, reg);
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if (ret)
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dev_err(dev, "Failed to set configuration\n");
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return ret;
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}
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static int opt4001_power_down(struct opt4001_chip *chip)
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{
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struct device *dev = &chip->client->dev;
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int ret;
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unsigned int reg;
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ret = regmap_read(chip->regmap, OPT4001_DEVICE_ID, ®);
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if (ret) {
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dev_err(dev, "Failed to read configuration\n");
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return ret;
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}
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/* MODE_OFF is 0x0 so just set bits to 0 */
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reg &= ~OPT4001_CTRL_OPER_MODE_MASK;
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ret = regmap_write(chip->regmap, OPT4001_CTRL, reg);
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if (ret)
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dev_err(dev, "Failed to set configuration to power down\n");
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return ret;
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}
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static void opt4001_chip_off_action(void *data)
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{
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struct opt4001_chip *chip = data;
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opt4001_power_down(chip);
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}
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static const struct iio_chan_spec opt4001_channels[] = {
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{
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.type = IIO_LIGHT,
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.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
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.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME),
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.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME)
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},
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};
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static int opt4001_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct opt4001_chip *chip = iio_priv(indio_dev);
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switch (mask) {
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case IIO_CHAN_INFO_PROCESSED:
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return opt4001_read_lux_value(indio_dev, val, val2);
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case IIO_CHAN_INFO_INT_TIME:
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*val = 0;
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*val2 = opt4001_int_time_reg[chip->int_time][0];
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return IIO_VAL_INT_PLUS_MICRO;
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default:
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return -EINVAL;
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}
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}
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static int opt4001_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask)
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{
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struct opt4001_chip *chip = iio_priv(indio_dev);
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int int_time;
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switch (mask) {
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case IIO_CHAN_INFO_INT_TIME:
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int_time = opt4001_als_time_to_index(val2);
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if (int_time < 0)
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return int_time;
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chip->int_time = int_time;
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return opt4001_set_conf(chip);
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default:
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return -EINVAL;
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}
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}
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static int opt4001_read_available(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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const int **vals, int *type, int *length,
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long mask)
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{
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switch (mask) {
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case IIO_CHAN_INFO_INT_TIME:
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*length = ARRAY_SIZE(opt4001_int_time_available) * 2;
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*vals = (const int *)opt4001_int_time_available;
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*type = IIO_VAL_INT_PLUS_MICRO;
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return IIO_AVAIL_LIST;
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default:
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return -EINVAL;
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}
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}
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static const struct iio_info opt4001_info_no_irq = {
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.read_raw = opt4001_read_raw,
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.write_raw = opt4001_write_raw,
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.read_avail = opt4001_read_available,
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};
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static int opt4001_load_defaults(struct opt4001_chip *chip)
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{
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chip->int_time = OPT4001_DEFAULT_CONVERSION_TIME;
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return opt4001_set_conf(chip);
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}
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static bool opt4001_readable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case OPT4001_LIGHT1_MSB:
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case OPT4001_LIGHT1_LSB:
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case OPT4001_CTRL:
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case OPT4001_DEVICE_ID:
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return true;
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default:
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return false;
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}
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}
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static bool opt4001_writable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case OPT4001_CTRL:
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return true;
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default:
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return false;
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}
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}
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static bool opt4001_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case OPT4001_LIGHT1_MSB:
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case OPT4001_LIGHT1_LSB:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config opt4001_regmap_config = {
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.name = "opt4001",
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.reg_bits = 8,
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.val_bits = 16,
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.cache_type = REGCACHE_RBTREE,
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.max_register = OPT4001_DEVICE_ID,
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.readable_reg = opt4001_readable_reg,
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.writeable_reg = opt4001_writable_reg,
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.volatile_reg = opt4001_volatile_reg,
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.val_format_endian = REGMAP_ENDIAN_BIG,
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};
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static int opt4001_probe(struct i2c_client *client)
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{
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struct opt4001_chip *chip;
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struct iio_dev *indio_dev;
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int ret;
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uint dev_id;
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indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
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if (!indio_dev)
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return -ENOMEM;
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chip = iio_priv(indio_dev);
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ret = devm_regulator_get_enable(&client->dev, "vdd");
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if (ret)
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return dev_err_probe(&client->dev, ret, "Failed to enable vdd supply\n");
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chip->regmap = devm_regmap_init_i2c(client, &opt4001_regmap_config);
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if (IS_ERR(chip->regmap))
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return dev_err_probe(&client->dev, PTR_ERR(chip->regmap),
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"regmap initialization failed\n");
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chip->client = client;
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indio_dev->info = &opt4001_info_no_irq;
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ret = regmap_reinit_cache(chip->regmap, &opt4001_regmap_config);
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if (ret)
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return dev_err_probe(&client->dev, ret,
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"failed to reinit regmap cache\n");
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ret = regmap_read(chip->regmap, OPT4001_DEVICE_ID, &dev_id);
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if (ret < 0)
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return dev_err_probe(&client->dev, ret,
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"Failed to read the device ID register\n");
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dev_id = FIELD_GET(OPT4001_DEVICE_ID_MASK, dev_id);
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if (dev_id != OPT4001_DEVICE_ID_VAL)
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||
|
dev_warn(&client->dev, "Device ID: %#04x unknown\n", dev_id);
|
||
|
|
||
|
chip->chip_info = i2c_get_match_data(client);
|
||
|
|
||
|
indio_dev->channels = opt4001_channels;
|
||
|
indio_dev->num_channels = ARRAY_SIZE(opt4001_channels);
|
||
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
||
|
indio_dev->name = chip->chip_info->name;
|
||
|
|
||
|
ret = opt4001_load_defaults(chip);
|
||
|
if (ret < 0)
|
||
|
return dev_err_probe(&client->dev, ret,
|
||
|
"Failed to set sensor defaults\n");
|
||
|
|
||
|
ret = devm_add_action_or_reset(&client->dev,
|
||
|
opt4001_chip_off_action,
|
||
|
chip);
|
||
|
if (ret < 0)
|
||
|
return dev_err_probe(&client->dev, ret,
|
||
|
"Failed to setup power off action\n");
|
||
|
|
||
|
return devm_iio_device_register(&client->dev, indio_dev);
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* The compatible string determines which constants to use depending on
|
||
|
* opt4001 packaging
|
||
|
*/
|
||
|
static const struct i2c_device_id opt4001_id[] = {
|
||
|
{ "opt4001-sot-5x3", (kernel_ulong_t)&opt4001_sot_5x3_info },
|
||
|
{ "opt4001-picostar", (kernel_ulong_t)&opt4001_picostar_info },
|
||
|
{ }
|
||
|
};
|
||
|
MODULE_DEVICE_TABLE(i2c, opt4001_id);
|
||
|
|
||
|
static const struct of_device_id opt4001_of_match[] = {
|
||
|
{ .compatible = "ti,opt4001-sot-5x3", .data = &opt4001_sot_5x3_info},
|
||
|
{ .compatible = "ti,opt4001-picostar", .data = &opt4001_picostar_info},
|
||
|
{}
|
||
|
};
|
||
|
MODULE_DEVICE_TABLE(of, opt4001_of_match);
|
||
|
|
||
|
static struct i2c_driver opt4001_driver = {
|
||
|
.driver = {
|
||
|
.name = "opt4001",
|
||
|
.of_match_table = opt4001_of_match,
|
||
|
},
|
||
|
.probe = opt4001_probe,
|
||
|
.id_table = opt4001_id,
|
||
|
};
|
||
|
module_i2c_driver(opt4001_driver);
|
||
|
|
||
|
MODULE_AUTHOR("Stefan Windfeldt-Prytz <stefan.windfeldt-prytz@axis.com>");
|
||
|
MODULE_DESCRIPTION("Texas Instruments opt4001 ambient light sensor driver");
|
||
|
MODULE_LICENSE("GPL");
|