118 lines
2.9 KiB
C
118 lines
2.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Intel Tangier GPIO functions
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*
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* Copyright (c) 2016, 2021, 2023 Intel Corporation.
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*
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* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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* Pandith N <pandith.n@intel.com>
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* Raag Jadav <raag.jadav@intel.com>
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*/
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#ifndef _GPIO_TANGIER_H_
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#define _GPIO_TANGIER_H_
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#include <linux/gpio/driver.h>
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#include <linux/pm.h>
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#include <linux/spinlock_types.h>
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#include <linux/types.h>
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struct device;
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struct tng_gpio_context;
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/* Elkhart Lake specific wake registers */
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#define GWMR_EHL 0x100 /* Wake mask */
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#define GWSR_EHL 0x118 /* Wake source */
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#define GSIR_EHL 0x130 /* Secure input */
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/* Merrifield specific wake registers */
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#define GWMR_MRFLD 0x400 /* Wake mask */
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#define GWSR_MRFLD 0x418 /* Wake source */
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#define GSIR_MRFLD 0xc00 /* Secure input */
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/**
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* struct tng_wake_regs - Platform specific wake registers
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* @gwmr: Wake mask
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* @gwsr: Wake source
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* @gsir: Secure input
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*/
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struct tng_wake_regs {
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u32 gwmr;
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u32 gwsr;
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u32 gsir;
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};
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/**
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* struct tng_gpio_pinrange - Map pin numbers to gpio numbers
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* @gpio_base: Starting GPIO number of this range
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* @pin_base: Starting pin number of this range
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* @npins: Number of pins in this range
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*/
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struct tng_gpio_pinrange {
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unsigned int gpio_base;
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unsigned int pin_base;
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unsigned int npins;
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};
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#define GPIO_PINRANGE(gstart, gend, pstart) \
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(struct tng_gpio_pinrange) { \
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.gpio_base = (gstart), \
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.pin_base = (pstart), \
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.npins = (gend) - (gstart) + 1, \
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}
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/**
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* struct tng_gpio_pin_info - Platform specific pinout information
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* @pin_ranges: Pin to GPIO mapping
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* @nranges: Number of pin ranges
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* @name: Respective pinctrl device name
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*/
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struct tng_gpio_pin_info {
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const struct tng_gpio_pinrange *pin_ranges;
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unsigned int nranges;
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const char *name;
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};
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/**
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* struct tng_gpio_info - Platform specific GPIO and IRQ information
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* @base: GPIO base to start numbering with
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* @ngpio: Amount of GPIOs supported by the controller
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* @first: First IRQ to start numbering with
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*/
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struct tng_gpio_info {
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int base;
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u16 ngpio;
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unsigned int first;
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};
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/**
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* struct tng_gpio - Platform specific private data
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* @chip: Instance of the struct gpio_chip
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* @reg_base: Base address of MMIO registers
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* @irq: Interrupt for the GPIO device
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* @lock: Synchronization lock to prevent I/O race conditions
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* @dev: The GPIO device
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* @ctx: Context to be saved during suspend-resume
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* @wake_regs: Platform specific wake registers
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* @pin_info: Platform specific pinout information
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* @info: Platform specific GPIO and IRQ information
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*/
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struct tng_gpio {
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struct gpio_chip chip;
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void __iomem *reg_base;
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int irq;
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raw_spinlock_t lock;
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struct device *dev;
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struct tng_gpio_context *ctx;
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struct tng_wake_regs wake_regs;
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struct tng_gpio_pin_info pin_info;
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struct tng_gpio_info info;
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};
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int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio);
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extern const struct dev_pm_ops tng_gpio_pm_ops;
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#endif /* _GPIO_TANGIER_H_ */
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