337 lines
8.0 KiB
C
337 lines
8.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* amlgoic-core.c - hardware cryptographic offloader for Amlogic GXL SoC
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*
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* Copyright (C) 2018-2019 Corentin Labbe <clabbe@baylibre.com>
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*
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* Core file which registers crypto algorithms supported by the hardware.
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*/
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#include <crypto/engine.h>
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#include <crypto/internal/skcipher.h>
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include "amlogic-gxl.h"
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static irqreturn_t meson_irq_handler(int irq, void *data)
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{
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struct meson_dev *mc = (struct meson_dev *)data;
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int flow;
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u32 p;
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for (flow = 0; flow < MAXFLOW; flow++) {
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if (mc->irqs[flow] == irq) {
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p = readl(mc->base + ((0x04 + flow) << 2));
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if (p) {
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writel_relaxed(0xF, mc->base + ((0x4 + flow) << 2));
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mc->chanlist[flow].status = 1;
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complete(&mc->chanlist[flow].complete);
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return IRQ_HANDLED;
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}
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dev_err(mc->dev, "%s %d Got irq for flow %d but ctrl is empty\n", __func__, irq, flow);
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}
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}
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dev_err(mc->dev, "%s %d from unknown irq\n", __func__, irq);
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return IRQ_HANDLED;
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}
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static struct meson_alg_template mc_algs[] = {
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{
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.type = CRYPTO_ALG_TYPE_SKCIPHER,
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.blockmode = MESON_OPMODE_CBC,
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.alg.skcipher.base = {
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.base = {
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.cra_name = "cbc(aes)",
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.cra_driver_name = "cbc-aes-gxl",
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.cra_priority = 400,
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.cra_blocksize = AES_BLOCK_SIZE,
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.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
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CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
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CRYPTO_ALG_NEED_FALLBACK,
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.cra_ctxsize = sizeof(struct meson_cipher_tfm_ctx),
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.cra_module = THIS_MODULE,
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.cra_alignmask = 0xf,
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.cra_init = meson_cipher_init,
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.cra_exit = meson_cipher_exit,
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},
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.min_keysize = AES_MIN_KEY_SIZE,
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.max_keysize = AES_MAX_KEY_SIZE,
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.ivsize = AES_BLOCK_SIZE,
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.setkey = meson_aes_setkey,
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.encrypt = meson_skencrypt,
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.decrypt = meson_skdecrypt,
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},
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.alg.skcipher.op = {
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.do_one_request = meson_handle_cipher_request,
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},
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},
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{
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.type = CRYPTO_ALG_TYPE_SKCIPHER,
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.blockmode = MESON_OPMODE_ECB,
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.alg.skcipher.base = {
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.base = {
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.cra_name = "ecb(aes)",
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.cra_driver_name = "ecb-aes-gxl",
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.cra_priority = 400,
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.cra_blocksize = AES_BLOCK_SIZE,
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.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
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CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
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CRYPTO_ALG_NEED_FALLBACK,
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.cra_ctxsize = sizeof(struct meson_cipher_tfm_ctx),
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.cra_module = THIS_MODULE,
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.cra_alignmask = 0xf,
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.cra_init = meson_cipher_init,
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.cra_exit = meson_cipher_exit,
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},
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.min_keysize = AES_MIN_KEY_SIZE,
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.max_keysize = AES_MAX_KEY_SIZE,
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.setkey = meson_aes_setkey,
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.encrypt = meson_skencrypt,
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.decrypt = meson_skdecrypt,
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},
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.alg.skcipher.op = {
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.do_one_request = meson_handle_cipher_request,
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},
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},
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};
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static int meson_debugfs_show(struct seq_file *seq, void *v)
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{
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struct meson_dev *mc __maybe_unused = seq->private;
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int i;
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for (i = 0; i < MAXFLOW; i++)
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seq_printf(seq, "Channel %d: nreq %lu\n", i,
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#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
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mc->chanlist[i].stat_req);
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#else
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0ul);
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#endif
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for (i = 0; i < ARRAY_SIZE(mc_algs); i++) {
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switch (mc_algs[i].type) {
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case CRYPTO_ALG_TYPE_SKCIPHER:
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seq_printf(seq, "%s %s %lu %lu\n",
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mc_algs[i].alg.skcipher.base.base.cra_driver_name,
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mc_algs[i].alg.skcipher.base.base.cra_name,
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#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
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mc_algs[i].stat_req, mc_algs[i].stat_fb);
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#else
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0ul, 0ul);
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#endif
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break;
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}
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}
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(meson_debugfs);
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static void meson_free_chanlist(struct meson_dev *mc, int i)
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{
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while (i >= 0) {
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crypto_engine_exit(mc->chanlist[i].engine);
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if (mc->chanlist[i].tl)
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dma_free_coherent(mc->dev, sizeof(struct meson_desc) * MAXDESC,
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mc->chanlist[i].tl,
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mc->chanlist[i].t_phy);
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i--;
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}
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}
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/*
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* Allocate the channel list structure
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*/
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static int meson_allocate_chanlist(struct meson_dev *mc)
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{
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int i, err;
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mc->chanlist = devm_kcalloc(mc->dev, MAXFLOW,
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sizeof(struct meson_flow), GFP_KERNEL);
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if (!mc->chanlist)
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return -ENOMEM;
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for (i = 0; i < MAXFLOW; i++) {
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init_completion(&mc->chanlist[i].complete);
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mc->chanlist[i].engine = crypto_engine_alloc_init(mc->dev, true);
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if (!mc->chanlist[i].engine) {
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dev_err(mc->dev, "Cannot allocate engine\n");
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i--;
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err = -ENOMEM;
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goto error_engine;
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}
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err = crypto_engine_start(mc->chanlist[i].engine);
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if (err) {
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dev_err(mc->dev, "Cannot start engine\n");
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goto error_engine;
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}
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mc->chanlist[i].tl = dma_alloc_coherent(mc->dev,
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sizeof(struct meson_desc) * MAXDESC,
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&mc->chanlist[i].t_phy,
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GFP_KERNEL);
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if (!mc->chanlist[i].tl) {
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err = -ENOMEM;
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goto error_engine;
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}
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}
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return 0;
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error_engine:
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meson_free_chanlist(mc, i);
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return err;
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}
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static int meson_register_algs(struct meson_dev *mc)
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{
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int err, i;
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for (i = 0; i < ARRAY_SIZE(mc_algs); i++) {
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mc_algs[i].mc = mc;
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switch (mc_algs[i].type) {
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case CRYPTO_ALG_TYPE_SKCIPHER:
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err = crypto_engine_register_skcipher(&mc_algs[i].alg.skcipher);
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if (err) {
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dev_err(mc->dev, "Fail to register %s\n",
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mc_algs[i].alg.skcipher.base.base.cra_name);
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mc_algs[i].mc = NULL;
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return err;
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}
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break;
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}
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}
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return 0;
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}
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static void meson_unregister_algs(struct meson_dev *mc)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mc_algs); i++) {
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if (!mc_algs[i].mc)
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continue;
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switch (mc_algs[i].type) {
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case CRYPTO_ALG_TYPE_SKCIPHER:
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crypto_engine_unregister_skcipher(&mc_algs[i].alg.skcipher);
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break;
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}
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}
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}
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static int meson_crypto_probe(struct platform_device *pdev)
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{
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struct meson_dev *mc;
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int err, i;
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mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
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if (!mc)
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return -ENOMEM;
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mc->dev = &pdev->dev;
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platform_set_drvdata(pdev, mc);
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mc->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mc->base)) {
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err = PTR_ERR(mc->base);
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dev_err(&pdev->dev, "Cannot request MMIO err=%d\n", err);
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return err;
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}
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mc->busclk = devm_clk_get(&pdev->dev, "blkmv");
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if (IS_ERR(mc->busclk)) {
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err = PTR_ERR(mc->busclk);
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dev_err(&pdev->dev, "Cannot get core clock err=%d\n", err);
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return err;
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}
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for (i = 0; i < MAXFLOW; i++) {
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mc->irqs[i] = platform_get_irq(pdev, i);
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if (mc->irqs[i] < 0)
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return mc->irqs[i];
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err = devm_request_irq(&pdev->dev, mc->irqs[i], meson_irq_handler, 0,
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"gxl-crypto", mc);
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if (err < 0) {
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dev_err(mc->dev, "Cannot request IRQ for flow %d\n", i);
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return err;
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}
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}
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err = clk_prepare_enable(mc->busclk);
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if (err != 0) {
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dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
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return err;
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}
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err = meson_allocate_chanlist(mc);
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if (err)
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goto error_flow;
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err = meson_register_algs(mc);
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if (err)
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goto error_alg;
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if (IS_ENABLED(CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG)) {
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struct dentry *dbgfs_dir;
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dbgfs_dir = debugfs_create_dir("gxl-crypto", NULL);
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debugfs_create_file("stats", 0444, dbgfs_dir, mc, &meson_debugfs_fops);
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#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
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mc->dbgfs_dir = dbgfs_dir;
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#endif
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}
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return 0;
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error_alg:
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meson_unregister_algs(mc);
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error_flow:
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meson_free_chanlist(mc, MAXFLOW - 1);
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clk_disable_unprepare(mc->busclk);
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return err;
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}
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static void meson_crypto_remove(struct platform_device *pdev)
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{
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struct meson_dev *mc = platform_get_drvdata(pdev);
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#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
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debugfs_remove_recursive(mc->dbgfs_dir);
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#endif
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meson_unregister_algs(mc);
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meson_free_chanlist(mc, MAXFLOW - 1);
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clk_disable_unprepare(mc->busclk);
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}
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static const struct of_device_id meson_crypto_of_match_table[] = {
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{ .compatible = "amlogic,gxl-crypto", },
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{}
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};
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MODULE_DEVICE_TABLE(of, meson_crypto_of_match_table);
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static struct platform_driver meson_crypto_driver = {
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.probe = meson_crypto_probe,
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.remove_new = meson_crypto_remove,
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.driver = {
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.name = "gxl-crypto",
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.of_match_table = meson_crypto_of_match_table,
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},
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};
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module_platform_driver(meson_crypto_driver);
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MODULE_DESCRIPTION("Amlogic GXL cryptographic offloader");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Corentin Labbe <clabbe@baylibre.com>");
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