267 lines
7.5 KiB
C
267 lines
7.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Clock driver for TPS68470 PMIC
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*
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* Copyright (c) 2021 Red Hat Inc.
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* Copyright (C) 2018 Intel Corporation
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*
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* Authors:
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* Hans de Goede <hdegoede@redhat.com>
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* Zaikuo Wang <zaikuo.wang@intel.com>
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* Tianshu Qiu <tian.shu.qiu@intel.com>
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* Jian Xu Zheng <jian.xu.zheng@intel.com>
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* Yuning Pu <yuning.pu@intel.com>
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* Antti Laakso <antti.laakso@intel.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/kernel.h>
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#include <linux/mfd/tps68470.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/tps68470.h>
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#include <linux/regmap.h>
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#define TPS68470_CLK_NAME "tps68470-clk"
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#define to_tps68470_clkdata(clkd) \
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container_of(clkd, struct tps68470_clkdata, clkout_hw)
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static struct tps68470_clkout_freqs {
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unsigned long freq;
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unsigned int xtaldiv;
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unsigned int plldiv;
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unsigned int postdiv;
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unsigned int buckdiv;
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unsigned int boostdiv;
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} clk_freqs[] = {
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/*
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* The PLL is used to multiply the crystal oscillator
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* frequency range of 3 MHz to 27 MHz by a programmable
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* factor of F = (M/N)*(1/P) such that the output
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* available at the HCLK_A or HCLK_B pins are in the range
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* of 4 MHz to 64 MHz in increments of 0.1 MHz.
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*
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* hclk_# = osc_in * (((plldiv*2)+320) / (xtaldiv+30)) * (1 / 2^postdiv)
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*
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* PLL_REF_CLK should be as close as possible to 100kHz
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* PLL_REF_CLK = input clk / XTALDIV[7:0] + 30)
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*
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* PLL_VCO_CLK = (PLL_REF_CLK * (plldiv*2 + 320))
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*
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* BOOST should be as close as possible to 2Mhz
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* BOOST = PLL_VCO_CLK / (BOOSTDIV[4:0] + 16) *
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*
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* BUCK should be as close as possible to 5.2Mhz
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* BUCK = PLL_VCO_CLK / (BUCKDIV[3:0] + 5)
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*
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* osc_in xtaldiv plldiv postdiv hclk_#
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* 20Mhz 170 32 1 19.2Mhz
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* 20Mhz 170 40 1 20Mhz
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* 20Mhz 170 80 1 24Mhz
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*/
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{ 19200000, 170, 32, 1, 2, 3 },
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{ 20000000, 170, 40, 1, 3, 4 },
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{ 24000000, 170, 80, 1, 4, 8 },
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};
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struct tps68470_clkdata {
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struct clk_hw clkout_hw;
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struct regmap *regmap;
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unsigned long rate;
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};
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static int tps68470_clk_is_prepared(struct clk_hw *hw)
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{
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struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
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int val;
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if (regmap_read(clkdata->regmap, TPS68470_REG_PLLCTL, &val))
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return 0;
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return val & TPS68470_PLL_EN_MASK;
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}
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static int tps68470_clk_prepare(struct clk_hw *hw)
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{
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struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
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regmap_write(clkdata->regmap, TPS68470_REG_CLKCFG1,
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(TPS68470_PLL_OUTPUT_ENABLE << TPS68470_OUTPUT_A_SHIFT) |
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(TPS68470_PLL_OUTPUT_ENABLE << TPS68470_OUTPUT_B_SHIFT));
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regmap_update_bits(clkdata->regmap, TPS68470_REG_PLLCTL,
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TPS68470_PLL_EN_MASK, TPS68470_PLL_EN_MASK);
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/*
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* The PLLCTL reg lock bit is set by the PMIC after approx. 4ms and
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* does not indicate a true lock, so just wait 4 ms.
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*/
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usleep_range(4000, 5000);
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return 0;
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}
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static void tps68470_clk_unprepare(struct clk_hw *hw)
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{
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struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
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/* Disable clock first ... */
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regmap_update_bits(clkdata->regmap, TPS68470_REG_PLLCTL, TPS68470_PLL_EN_MASK, 0);
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/* ... and then tri-state the clock outputs. */
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regmap_write(clkdata->regmap, TPS68470_REG_CLKCFG1, 0);
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}
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static unsigned long tps68470_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
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return clkdata->rate;
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}
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/*
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* This returns the index of the clk_freqs[] cfg with the closest rate for
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* use in tps68470_clk_round_rate(). tps68470_clk_set_rate() checks that
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* the rate of the returned cfg is an exact match.
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*/
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static unsigned int tps68470_clk_cfg_lookup(unsigned long rate)
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{
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long diff, best_diff = LONG_MAX;
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unsigned int i, best_idx = 0;
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for (i = 0; i < ARRAY_SIZE(clk_freqs); i++) {
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diff = clk_freqs[i].freq - rate;
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if (diff == 0)
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return i;
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diff = abs(diff);
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if (diff < best_diff) {
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best_diff = diff;
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best_idx = i;
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}
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}
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return best_idx;
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}
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static long tps68470_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned int idx = tps68470_clk_cfg_lookup(rate);
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return clk_freqs[idx].freq;
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}
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static int tps68470_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
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unsigned int idx = tps68470_clk_cfg_lookup(rate);
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if (rate != clk_freqs[idx].freq)
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return -EINVAL;
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regmap_write(clkdata->regmap, TPS68470_REG_BOOSTDIV, clk_freqs[idx].boostdiv);
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regmap_write(clkdata->regmap, TPS68470_REG_BUCKDIV, clk_freqs[idx].buckdiv);
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regmap_write(clkdata->regmap, TPS68470_REG_PLLSWR, TPS68470_PLLSWR_DEFAULT);
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regmap_write(clkdata->regmap, TPS68470_REG_XTALDIV, clk_freqs[idx].xtaldiv);
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regmap_write(clkdata->regmap, TPS68470_REG_PLLDIV, clk_freqs[idx].plldiv);
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regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV, clk_freqs[idx].postdiv);
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regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV2, clk_freqs[idx].postdiv);
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regmap_write(clkdata->regmap, TPS68470_REG_CLKCFG2, TPS68470_CLKCFG2_DRV_STR_2MA);
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regmap_write(clkdata->regmap, TPS68470_REG_PLLCTL,
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TPS68470_OSC_EXT_CAP_DEFAULT << TPS68470_OSC_EXT_CAP_SHIFT |
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TPS68470_CLK_SRC_XTAL << TPS68470_CLK_SRC_SHIFT);
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clkdata->rate = rate;
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return 0;
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}
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static const struct clk_ops tps68470_clk_ops = {
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.is_prepared = tps68470_clk_is_prepared,
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.prepare = tps68470_clk_prepare,
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.unprepare = tps68470_clk_unprepare,
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.recalc_rate = tps68470_clk_recalc_rate,
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.round_rate = tps68470_clk_round_rate,
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.set_rate = tps68470_clk_set_rate,
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};
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static int tps68470_clk_probe(struct platform_device *pdev)
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{
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struct tps68470_clk_platform_data *pdata = pdev->dev.platform_data;
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struct clk_init_data tps68470_clk_initdata = {
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.name = TPS68470_CLK_NAME,
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.ops = &tps68470_clk_ops,
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/* Changing the dividers when the PLL is on is not allowed */
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.flags = CLK_SET_RATE_GATE,
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};
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struct tps68470_clkdata *tps68470_clkdata;
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struct tps68470_clk_consumer *consumer;
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int ret;
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int i;
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tps68470_clkdata = devm_kzalloc(&pdev->dev, sizeof(*tps68470_clkdata),
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GFP_KERNEL);
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if (!tps68470_clkdata)
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return -ENOMEM;
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tps68470_clkdata->regmap = dev_get_drvdata(pdev->dev.parent);
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tps68470_clkdata->clkout_hw.init = &tps68470_clk_initdata;
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/* Set initial rate */
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tps68470_clk_set_rate(&tps68470_clkdata->clkout_hw, clk_freqs[0].freq, 0);
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ret = devm_clk_hw_register(&pdev->dev, &tps68470_clkdata->clkout_hw);
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if (ret)
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return ret;
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ret = devm_clk_hw_register_clkdev(&pdev->dev, &tps68470_clkdata->clkout_hw,
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TPS68470_CLK_NAME, NULL);
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if (ret)
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return ret;
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if (pdata) {
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for (i = 0; i < pdata->n_consumers; i++) {
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consumer = &pdata->consumers[i];
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ret = devm_clk_hw_register_clkdev(&pdev->dev,
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&tps68470_clkdata->clkout_hw,
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consumer->consumer_con_id,
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consumer->consumer_dev_name);
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}
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}
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return ret;
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}
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static struct platform_driver tps68470_clk_driver = {
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.driver = {
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.name = TPS68470_CLK_NAME,
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},
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.probe = tps68470_clk_probe,
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};
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/*
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* The ACPI tps68470 probe-ordering depends on the clk/gpio/regulator drivers
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* registering before the drivers for the camera-sensors which use them bind.
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* subsys_initcall() ensures this when the drivers are builtin.
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*/
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static int __init tps68470_clk_init(void)
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{
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return platform_driver_register(&tps68470_clk_driver);
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}
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subsys_initcall(tps68470_clk_init);
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static void __exit tps68470_clk_exit(void)
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{
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platform_driver_unregister(&tps68470_clk_driver);
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}
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module_exit(tps68470_clk_exit);
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MODULE_ALIAS("platform:tps68470-clk");
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MODULE_DESCRIPTION("clock driver for TPS68470 pmic");
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MODULE_LICENSE("GPL");
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