317 lines
7.5 KiB
C
317 lines
7.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/perf_event.h>
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#include <linux/sysfs.h>
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#include <linux/nospec.h>
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#include <asm/intel-family.h>
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#include "probe.h"
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enum perf_msr_id {
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PERF_MSR_TSC = 0,
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PERF_MSR_APERF = 1,
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PERF_MSR_MPERF = 2,
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PERF_MSR_PPERF = 3,
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PERF_MSR_SMI = 4,
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PERF_MSR_PTSC = 5,
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PERF_MSR_IRPERF = 6,
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PERF_MSR_THERM = 7,
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PERF_MSR_EVENT_MAX,
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};
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static bool test_aperfmperf(int idx, void *data)
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{
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return boot_cpu_has(X86_FEATURE_APERFMPERF);
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}
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static bool test_ptsc(int idx, void *data)
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{
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return boot_cpu_has(X86_FEATURE_PTSC);
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}
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static bool test_irperf(int idx, void *data)
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{
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return boot_cpu_has(X86_FEATURE_IRPERF);
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}
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static bool test_therm_status(int idx, void *data)
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{
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return boot_cpu_has(X86_FEATURE_DTHERM);
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}
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static bool test_intel(int idx, void *data)
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{
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if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
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boot_cpu_data.x86 != 6)
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return false;
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switch (boot_cpu_data.x86_model) {
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case INTEL_FAM6_NEHALEM:
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case INTEL_FAM6_NEHALEM_G:
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case INTEL_FAM6_NEHALEM_EP:
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case INTEL_FAM6_NEHALEM_EX:
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case INTEL_FAM6_WESTMERE:
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case INTEL_FAM6_WESTMERE_EP:
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case INTEL_FAM6_WESTMERE_EX:
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case INTEL_FAM6_SANDYBRIDGE:
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case INTEL_FAM6_SANDYBRIDGE_X:
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case INTEL_FAM6_IVYBRIDGE:
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case INTEL_FAM6_IVYBRIDGE_X:
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case INTEL_FAM6_HASWELL:
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case INTEL_FAM6_HASWELL_X:
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case INTEL_FAM6_HASWELL_L:
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case INTEL_FAM6_HASWELL_G:
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case INTEL_FAM6_BROADWELL:
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case INTEL_FAM6_BROADWELL_D:
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case INTEL_FAM6_BROADWELL_G:
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case INTEL_FAM6_BROADWELL_X:
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case INTEL_FAM6_SAPPHIRERAPIDS_X:
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case INTEL_FAM6_EMERALDRAPIDS_X:
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case INTEL_FAM6_GRANITERAPIDS_X:
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case INTEL_FAM6_GRANITERAPIDS_D:
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case INTEL_FAM6_ATOM_SILVERMONT:
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case INTEL_FAM6_ATOM_SILVERMONT_D:
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case INTEL_FAM6_ATOM_AIRMONT:
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case INTEL_FAM6_ATOM_GOLDMONT:
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case INTEL_FAM6_ATOM_GOLDMONT_D:
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case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
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case INTEL_FAM6_ATOM_TREMONT_D:
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case INTEL_FAM6_ATOM_TREMONT:
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case INTEL_FAM6_ATOM_TREMONT_L:
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case INTEL_FAM6_XEON_PHI_KNL:
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case INTEL_FAM6_XEON_PHI_KNM:
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if (idx == PERF_MSR_SMI)
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return true;
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break;
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case INTEL_FAM6_SKYLAKE_L:
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case INTEL_FAM6_SKYLAKE:
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case INTEL_FAM6_SKYLAKE_X:
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case INTEL_FAM6_KABYLAKE_L:
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case INTEL_FAM6_KABYLAKE:
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case INTEL_FAM6_COMETLAKE_L:
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case INTEL_FAM6_COMETLAKE:
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case INTEL_FAM6_ICELAKE_L:
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case INTEL_FAM6_ICELAKE:
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case INTEL_FAM6_ICELAKE_X:
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case INTEL_FAM6_ICELAKE_D:
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case INTEL_FAM6_TIGERLAKE_L:
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case INTEL_FAM6_TIGERLAKE:
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case INTEL_FAM6_ROCKETLAKE:
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case INTEL_FAM6_ALDERLAKE:
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case INTEL_FAM6_ALDERLAKE_L:
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case INTEL_FAM6_ATOM_GRACEMONT:
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case INTEL_FAM6_RAPTORLAKE:
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case INTEL_FAM6_RAPTORLAKE_P:
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case INTEL_FAM6_RAPTORLAKE_S:
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case INTEL_FAM6_METEORLAKE:
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case INTEL_FAM6_METEORLAKE_L:
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if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
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return true;
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break;
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}
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return false;
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}
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PMU_EVENT_ATTR_STRING(tsc, attr_tsc, "event=0x00" );
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PMU_EVENT_ATTR_STRING(aperf, attr_aperf, "event=0x01" );
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PMU_EVENT_ATTR_STRING(mperf, attr_mperf, "event=0x02" );
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PMU_EVENT_ATTR_STRING(pperf, attr_pperf, "event=0x03" );
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PMU_EVENT_ATTR_STRING(smi, attr_smi, "event=0x04" );
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PMU_EVENT_ATTR_STRING(ptsc, attr_ptsc, "event=0x05" );
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PMU_EVENT_ATTR_STRING(irperf, attr_irperf, "event=0x06" );
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PMU_EVENT_ATTR_STRING(cpu_thermal_margin, attr_therm, "event=0x07" );
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PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot, attr_therm_snap, "1" );
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PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit, attr_therm_unit, "C" );
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static unsigned long msr_mask;
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PMU_EVENT_GROUP(events, aperf);
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PMU_EVENT_GROUP(events, mperf);
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PMU_EVENT_GROUP(events, pperf);
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PMU_EVENT_GROUP(events, smi);
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PMU_EVENT_GROUP(events, ptsc);
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PMU_EVENT_GROUP(events, irperf);
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static struct attribute *attrs_therm[] = {
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&attr_therm.attr.attr,
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&attr_therm_snap.attr.attr,
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&attr_therm_unit.attr.attr,
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NULL,
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};
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static struct attribute_group group_therm = {
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.name = "events",
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.attrs = attrs_therm,
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};
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static struct perf_msr msr[] = {
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[PERF_MSR_TSC] = { .no_check = true, },
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[PERF_MSR_APERF] = { MSR_IA32_APERF, &group_aperf, test_aperfmperf, },
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[PERF_MSR_MPERF] = { MSR_IA32_MPERF, &group_mperf, test_aperfmperf, },
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[PERF_MSR_PPERF] = { MSR_PPERF, &group_pperf, test_intel, },
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[PERF_MSR_SMI] = { MSR_SMI_COUNT, &group_smi, test_intel, },
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[PERF_MSR_PTSC] = { MSR_F15H_PTSC, &group_ptsc, test_ptsc, },
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[PERF_MSR_IRPERF] = { MSR_F17H_IRPERF, &group_irperf, test_irperf, },
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[PERF_MSR_THERM] = { MSR_IA32_THERM_STATUS, &group_therm, test_therm_status, },
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};
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static struct attribute *events_attrs[] = {
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&attr_tsc.attr.attr,
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NULL,
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};
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static struct attribute_group events_attr_group = {
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.name = "events",
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.attrs = events_attrs,
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};
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PMU_FORMAT_ATTR(event, "config:0-63");
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static struct attribute *format_attrs[] = {
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&format_attr_event.attr,
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NULL,
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};
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static struct attribute_group format_attr_group = {
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.name = "format",
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.attrs = format_attrs,
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};
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static const struct attribute_group *attr_groups[] = {
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&events_attr_group,
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&format_attr_group,
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NULL,
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};
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static const struct attribute_group *attr_update[] = {
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&group_aperf,
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&group_mperf,
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&group_pperf,
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&group_smi,
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&group_ptsc,
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&group_irperf,
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&group_therm,
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NULL,
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};
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static int msr_event_init(struct perf_event *event)
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{
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u64 cfg = event->attr.config;
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if (event->attr.type != event->pmu->type)
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return -ENOENT;
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/* unsupported modes and filters */
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if (event->attr.sample_period) /* no sampling */
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return -EINVAL;
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if (cfg >= PERF_MSR_EVENT_MAX)
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return -EINVAL;
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cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX);
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if (!(msr_mask & (1 << cfg)))
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return -EINVAL;
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event->hw.idx = -1;
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event->hw.event_base = msr[cfg].msr;
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event->hw.config = cfg;
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return 0;
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}
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static inline u64 msr_read_counter(struct perf_event *event)
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{
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u64 now;
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if (event->hw.event_base)
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rdmsrl(event->hw.event_base, now);
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else
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now = rdtsc_ordered();
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return now;
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}
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static void msr_event_update(struct perf_event *event)
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{
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u64 prev, now;
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s64 delta;
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/* Careful, an NMI might modify the previous event value: */
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prev = local64_read(&event->hw.prev_count);
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do {
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now = msr_read_counter(event);
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} while (!local64_try_cmpxchg(&event->hw.prev_count, &prev, now));
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delta = now - prev;
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if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
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delta = sign_extend64(delta, 31);
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local64_add(delta, &event->count);
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} else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) {
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/* If valid, extract digital readout, otherwise set to -1: */
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now = now & (1ULL << 31) ? (now >> 16) & 0x3f : -1;
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local64_set(&event->count, now);
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} else {
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local64_add(delta, &event->count);
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}
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}
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static void msr_event_start(struct perf_event *event, int flags)
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{
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u64 now = msr_read_counter(event);
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local64_set(&event->hw.prev_count, now);
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}
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static void msr_event_stop(struct perf_event *event, int flags)
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{
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msr_event_update(event);
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}
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static void msr_event_del(struct perf_event *event, int flags)
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{
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msr_event_stop(event, PERF_EF_UPDATE);
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}
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static int msr_event_add(struct perf_event *event, int flags)
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{
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if (flags & PERF_EF_START)
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msr_event_start(event, flags);
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return 0;
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}
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static struct pmu pmu_msr = {
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.task_ctx_nr = perf_sw_context,
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.attr_groups = attr_groups,
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.event_init = msr_event_init,
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.add = msr_event_add,
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.del = msr_event_del,
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.start = msr_event_start,
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.stop = msr_event_stop,
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.read = msr_event_update,
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.capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
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.attr_update = attr_update,
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};
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static int __init msr_init(void)
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{
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if (!boot_cpu_has(X86_FEATURE_TSC)) {
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pr_cont("no MSR PMU driver.\n");
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return 0;
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}
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msr_mask = perf_msr_probe(msr, PERF_MSR_EVENT_MAX, true, NULL);
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perf_pmu_register(&pmu_msr, "msr", -1);
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return 0;
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}
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device_initcall(msr_init);
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