322 lines
8.1 KiB
C
322 lines
8.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Processor capabilities determination functions.
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*
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* Copyright (C) xxxx the Anonymous
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* Copyright (C) 1994 - 2006 Ralf Baechle
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* Copyright (C) 2003, 2004 Maciej W. Rozycki
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* Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/bugs.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm/cpu-type.h>
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#include <asm/elf.h>
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#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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#include "fpu-probe.h"
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/*
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* Get the FPU Implementation/Revision.
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*/
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static inline unsigned long cpu_get_fpu_id(void)
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{
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unsigned long tmp, fpu_id;
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tmp = read_c0_status();
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__enable_fpu(FPU_AS_IS);
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fpu_id = read_32bit_cp1_register(CP1_REVISION);
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write_c0_status(tmp);
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return fpu_id;
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}
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/*
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* Check if the CPU has an external FPU.
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*/
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int __cpu_has_fpu(void)
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{
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return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
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}
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/*
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* Determine the FCSR mask for FPU hardware.
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*/
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static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
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{
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unsigned long sr, mask, fcsr, fcsr0, fcsr1;
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fcsr = c->fpu_csr31;
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mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
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sr = read_c0_status();
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__enable_fpu(FPU_AS_IS);
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fcsr0 = fcsr & mask;
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write_32bit_cp1_register(CP1_STATUS, fcsr0);
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fcsr0 = read_32bit_cp1_register(CP1_STATUS);
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fcsr1 = fcsr | ~mask;
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write_32bit_cp1_register(CP1_STATUS, fcsr1);
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fcsr1 = read_32bit_cp1_register(CP1_STATUS);
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write_32bit_cp1_register(CP1_STATUS, fcsr);
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write_c0_status(sr);
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c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
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}
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/*
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* Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
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* supported by FPU hardware.
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*/
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static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
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{
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if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
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MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
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MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
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MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
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unsigned long sr, fir, fcsr, fcsr0, fcsr1;
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sr = read_c0_status();
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__enable_fpu(FPU_AS_IS);
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fir = read_32bit_cp1_register(CP1_REVISION);
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if (fir & MIPS_FPIR_HAS2008) {
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fcsr = read_32bit_cp1_register(CP1_STATUS);
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/*
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* MAC2008 toolchain never landed in real world, so
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* we're only testing whether it can be disabled and
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* don't try to enabled it.
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*/
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fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008 |
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FPU_CSR_MAC2008);
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write_32bit_cp1_register(CP1_STATUS, fcsr0);
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fcsr0 = read_32bit_cp1_register(CP1_STATUS);
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fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
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write_32bit_cp1_register(CP1_STATUS, fcsr1);
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fcsr1 = read_32bit_cp1_register(CP1_STATUS);
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write_32bit_cp1_register(CP1_STATUS, fcsr);
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if (c->isa_level & (MIPS_CPU_ISA_M32R2 |
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MIPS_CPU_ISA_M64R2)) {
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/*
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* The bit for MAC2008 might be reused by R6
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* in future, so we only test for R2-R5.
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*/
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if (fcsr0 & FPU_CSR_MAC2008)
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c->options |= MIPS_CPU_MAC_2008_ONLY;
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}
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if (!(fcsr0 & FPU_CSR_NAN2008))
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c->options |= MIPS_CPU_NAN_LEGACY;
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if (fcsr1 & FPU_CSR_NAN2008)
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c->options |= MIPS_CPU_NAN_2008;
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if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
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c->fpu_msk31 &= ~FPU_CSR_ABS2008;
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else
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c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
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if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
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c->fpu_msk31 &= ~FPU_CSR_NAN2008;
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else
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c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
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} else {
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c->options |= MIPS_CPU_NAN_LEGACY;
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}
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write_c0_status(sr);
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} else {
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c->options |= MIPS_CPU_NAN_LEGACY;
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}
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}
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/*
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* IEEE 754 conformance mode to use. Affects the NaN encoding and the
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* ABS.fmt/NEG.fmt execution mode.
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*/
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static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
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/*
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* Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
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* to support by the FPU emulator according to the IEEE 754 conformance
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* mode selected. Note that "relaxed" straps the emulator so that it
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* allows 2008-NaN binaries even for legacy processors.
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*/
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static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
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{
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c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
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c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
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c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
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switch (ieee754) {
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case STRICT:
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if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
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MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
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MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
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MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
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c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
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} else {
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c->options |= MIPS_CPU_NAN_LEGACY;
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c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
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}
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break;
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case LEGACY:
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c->options |= MIPS_CPU_NAN_LEGACY;
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c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
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break;
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case STD2008:
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c->options |= MIPS_CPU_NAN_2008;
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c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
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c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
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break;
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case RELAXED:
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c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
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break;
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}
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}
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/*
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* Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
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* according to the "ieee754=" parameter.
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*/
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static void cpu_set_nan_2008(struct cpuinfo_mips *c)
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{
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switch (ieee754) {
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case STRICT:
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mips_use_nan_legacy = !!cpu_has_nan_legacy;
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mips_use_nan_2008 = !!cpu_has_nan_2008;
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break;
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case LEGACY:
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mips_use_nan_legacy = !!cpu_has_nan_legacy;
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mips_use_nan_2008 = !cpu_has_nan_legacy;
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break;
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case STD2008:
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mips_use_nan_legacy = !cpu_has_nan_2008;
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mips_use_nan_2008 = !!cpu_has_nan_2008;
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break;
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case RELAXED:
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mips_use_nan_legacy = true;
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mips_use_nan_2008 = true;
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break;
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}
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}
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/*
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* IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
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* settings:
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*
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* strict: accept binaries that request a NaN encoding supported by the FPU
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* legacy: only accept legacy-NaN binaries
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* 2008: only accept 2008-NaN binaries
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* relaxed: accept any binaries regardless of whether supported by the FPU
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*/
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static int __init ieee754_setup(char *s)
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{
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if (!s)
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return -1;
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else if (!strcmp(s, "strict"))
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ieee754 = STRICT;
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else if (!strcmp(s, "legacy"))
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ieee754 = LEGACY;
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else if (!strcmp(s, "2008"))
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ieee754 = STD2008;
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else if (!strcmp(s, "relaxed"))
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ieee754 = RELAXED;
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else
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return -1;
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if (!(boot_cpu_data.options & MIPS_CPU_FPU))
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cpu_set_nofpu_2008(&boot_cpu_data);
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cpu_set_nan_2008(&boot_cpu_data);
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return 0;
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}
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early_param("ieee754", ieee754_setup);
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/*
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* Set the FIR feature flags for the FPU emulator.
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*/
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static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
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{
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u32 value;
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value = 0;
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if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
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MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
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MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
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MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
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value |= MIPS_FPIR_D | MIPS_FPIR_S;
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if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
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MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
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MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
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value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
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if (c->options & MIPS_CPU_NAN_2008)
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value |= MIPS_FPIR_HAS2008;
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c->fpu_id = value;
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}
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/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
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static unsigned int mips_nofpu_msk31;
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/*
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* Set options for FPU hardware.
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*/
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void cpu_set_fpu_opts(struct cpuinfo_mips *c)
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{
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c->fpu_id = cpu_get_fpu_id();
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mips_nofpu_msk31 = c->fpu_msk31;
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if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
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MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
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MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
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MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
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if (c->fpu_id & MIPS_FPIR_3D)
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c->ases |= MIPS_ASE_MIPS3D;
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if (c->fpu_id & MIPS_FPIR_UFRP)
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c->options |= MIPS_CPU_UFR;
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if (c->fpu_id & MIPS_FPIR_FREP)
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c->options |= MIPS_CPU_FRE;
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}
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cpu_set_fpu_fcsr_mask(c);
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cpu_set_fpu_2008(c);
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cpu_set_nan_2008(c);
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}
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/*
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* Set options for the FPU emulator.
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*/
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void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
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{
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c->options &= ~MIPS_CPU_FPU;
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c->fpu_msk31 = mips_nofpu_msk31;
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cpu_set_nofpu_2008(c);
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cpu_set_nan_2008(c);
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cpu_set_nofpu_id(c);
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}
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int mips_fpu_disabled;
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static int __init fpu_disable(char *s)
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{
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cpu_set_nofpu_opts(&boot_cpu_data);
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mips_fpu_disabled = 1;
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return 1;
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}
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__setup("nofpu", fpu_disable);
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